Split GPU+FPGA to separate training modules. (#56)

* Update SridharaDasu.md

* Update SridharaDasu.md

* Pulled the original from tac-hep site

* Removed FPGA modules

* Updated FPGA part

pages/training-modules.md

@@ -11,7 +11,8 @@ title: Training Modules
 #### List of trainings
 
 * [Software Engineering for Scientific Computing](/training-modules/software-engineering)
-* [GPU and FPGA training module](/training-modules/uw-gpu-fpga)
+* [GPU training module](/training-modules/uw-gpu)
+* [FPGA training module](/training-modules/uw-fpga)
 * [Data Analysis Systems and Facilities](/training-modules/analysis-systems-and-facilities)
 * [Scalable Infrastructure](/training-modules/scalable-infrastructure)
 

pages/training-modules/uw-fpga.md

@@ -0,0 +1,27 @@
+---
+permalink: /training-modules/uw-fpga.html
+layout: default
+title: FPGA training
+---
+
+# FPGA training module 
+<p align="justify">
+This training module aims to introduce the students to the concept of FPGAs, programming them using a higher level language (C++) and synthesizing firmware. We use Xilinx platform.
+The duration of this training is 1 semester (14 weeks). The detailed syllabus and series of lectures can be found below.
+</p>
+- [Course syllabus]({{ site.baseurl }}/training-modules/uw-fpga/syllabus)
+- Series of lectures :
+  - [Lecture 1]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-21-FPGA-HLS-Lecture-1.pdf) Introduction to FPGA and its architecture
+  - [Lecture 2]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-22-FPGA-HLS-Lecture-2.pdf) FPGA: Parallelism in program execution
+  - [Lecture 3]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-28-FPGA-HLS-Lecture-3.pdf) FPGA: Clock Frequency, Latency, Pipelining
+  - [Lecture 4]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-29-FPGA-HLS-Lecture-4.pdf) Introduction to Vivado HLS, Setup
+  - [Lecture 5]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-04-FPGA-HLS-Lecture-5.pdf) Hands-on with vivado_hls, output review
+  - [Lecture 6]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-05-FPGA-HLS-Lecture-6.pdf) Hands-on with vivado_hls, Introduction to Pragmas
+  - [Lecture 7]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-11-FPGA-HLS-Lecture-7.pdf) Vivado HLS: Pragmas & more examples
+  - [Lecture 8]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-12-FPGA-HLS-Lecture-8.pdf) Vivado HLS: Pragma’s effect on performance
+  - [Lecture 9]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-18-FPGA-HLS-Lecture-9.pdf) Vivado HLS: More pragmas and Do’s & Don’ts
+  - [Lecture 10]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-19-FPGA-HLS-Lecture-10.pdf) Vivado HLS: More pragmas and HLS coding styles
+  - [Lecture 11]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-25-FPGA-HLS-Lecture-11.pdf) LHC, CMS Level-1 Trigger, Project
+  - [Lecture 12]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-26-FPGA-HLS-Lecture-12.pdf) Project: Re-designing RCT
+  - [Lecture 13]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-05-02-FPGA-HLS-Lecture-13.pdf) Introduction to VHDL
+  - [Lecture 14]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-05-03-FPGA-HLS-Lecture-14.pdf) Introduction to VHDL contd.

pages/training-modules/uw-fpga/syllabus.md

@@ -0,0 +1,100 @@
+---
+permalink: /training-modules/uw-fpga/syllabus.html
+layout: default
+title: Course syllabus
+---
+
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>INSTITUTION NAME:</strong></span> University of Wisconsin&ndash;Madison</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>COURSE SUBJECT, NUMBER AND TITLE: </strong></span>TAC-HEP : FPGA training module&nbsp;</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>CREDITS:</strong></span> 3 credits equivalent</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>COURSE DESCRIPTION:</strong></span></p>
+<p style="text-align: justify;">Introduction to FPGA programming. Overview of FPGA, design flow, introduction High-Level synthesis and its applications</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>REQUISITES:</strong></span></p>
+<ul>
+<li>Familiarity navigating through UNIX based OS. Familiarity with CLI. Elementary knowledge of C or C++.</li>
+<li>Students need to set-up a Wisconsin computing account and have login access to cmstrigger01 machine with Xilinx Vivado tools. Students will be provided instructions for doing so prior to the start of the training.</li>
+</ul>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>MEETING TIME AND LOCATION:</strong></span></p>
+<p style="text-align: justify;"><span style="text-decoration: underline;"><strong>Zoom coordinates:&nbsp;</strong></span></p>
+<p style="text-align: justify;"><a href="https://cern.zoom.us/j/69712006717?pwd=c0pqUGZxbUlFNkVRSWxHc24yL21tdz09" target="_blank" rel="noopener">https://cern.zoom.us/j/69712006717?pwd=c0pqUGZxbUlFNkVRSWxHc24yL21tdz09</a></p>
+<p style="text-align: justify;">Meeting ID: 697 1200 6717</p>
+
+<p style="text-align: justify;"><strong>FPGA Module</strong></p>
+<p style="text-align: justify;">Lectures: Tuesdays and Wednesday: 9:00 &ndash; 10:00 AM (CT), 10:00 &ndash; 11:00 AM (EST), 16:00 &ndash; 17:00 PM (CERN) via zoom</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>INSTRUCTIONAL MODALITY:</strong></span></p>
+<p style="text-align: justify;">Virtual via zoom. There will be a combination of lectures and hands-on training.</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>OFFICE HOURS:</strong></span></p>
+<ul>
+<li>Office hours by appointment.&nbsp;</li>
+<li>Slack channel to post questions and communicate with instructors :</li>
+<ul>
+<li><a href="https://uwmadisoncms.slack.com/archives/C04JCTY6SAH" target="_blank" rel="noopener">https://uwmadisoncms.slack.com/archives/C04JCTY6SAH</a></li>
+</ul>
+</ul>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>INSTRUCTOR CONTACT INFO:</strong></span></p>
+<p style="text-align: justify;">Dr. Varun Sharma</p>
+<p style="text-align: justify;"><a href="mailto:[email protected]" target="_blank" rel="noopener">[email protected]</a></p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>COURSE LEARNING OUTCOMES:</strong></span></p>
+<p style="text-align: justify;">Develop an understanding of the differences between different hardware (CPUs / GPUs / FPGAs). Get familiar with their use cases in HEP and develop the ability to identify the ideal hardware accelerator for different HEP applications. Understand the role and capabilities of FPGAs and High Level Synthesis, and learn to write algorithms for hardware.</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>COURSE OVERVIEW:</strong></span></p>
+<p style="text-align: justify;">REQUIRED TEXTBOOK, SOFTWARE AND OTHER COURSE MATERIALS:</p>
+<ul>
+<li>No required textbook</li>
+<li>All softwares will be installed in the available machines</li>
+</ul>
+<p>HLS manual for reference:&nbsp; &nbsp; &nbsp; &nbsp; <a href="https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf" target="_blank" rel="noopener">https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf</a></p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>HOMEWORK AND OTHER ASSIGNMENTS:</strong></span></p>
+<p style="text-align: justify;">Week 1-7: Weekly assignments&nbsp;</p>
+<p style="text-align: justify;">Week 8-14: Project</p>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>GRADING:</strong></span></p>
+<div>
+<table>
+<tbody>
+<tr>
+<td><strong>Weekly assignments&nbsp;</strong></td>
+<td>50%</td>
+</tr>
+<tr>
+<td><strong>Final project</strong></td>
+<td>50%</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>COURSE SCHEDULE/CALENDAR</strong></span></p>
+<p style="text-align: justify;"><strong>Deadlines:</strong></p>
+<ul>
+<li>Each weekly assignment is due Friday of the next week&nbsp;</li>
+<li>Final project is due end (by Sunday) of week 14, Friday April 30th.</li>
+</ul>
+<p style="text-align: justify;"><span style="color: #cc0000;"><strong>TOPICS COVERED</strong></span></p>
+<h4 style="text-align: justify;">Week 1</h4>
+<ul>
+<li>FPGA &ndash; Introduction, why do we need them? different options available in market;</li>
+<li>Overview of FPGA architecture, programming model and FPGA parallelism vs processor architectures</li>
+</ul>
+<h4 style="text-align: justify;">Week 2</h4>
+<ul>
+<li>Digital systems: some important components used on the FPGAs like registers (flip-flops), DSPs, LUTs;</li>
+<li>Basic concepts of Hardware design: Clock Frequency, Latency and Pipelining, Throughput</li>
+</ul>
+
+<h4 style="text-align: justify;">Week 3-4</h4>
+<ul>
+<li>Vivado High-level Synthesis (HLS): Basic overview, understanding of HLS, its purpose, benefit and usage;</li>
+<li>Mathematical Operations, Conditional statements, Loops, functions in HLS</li>
+<li>HLS: Linear Algebra library functions, DSP library functions, C++ arbitrary precision types, datatypes for efficient hardware, Design analysis and optimisation and RTL verification;</li>
+<li>Case study of trigger algorithms developed for the LHC experiments</li>
+<li> Introduction to CMS experiment and Level-1 Trigger system</li>
+<li>Basic introduction to VHDL and design flow</li>
+<li>Quick introduction and guide to HLS4ML</li>
+</ul>
+
+<h4 style="text-align: justify;">Week 5-6-7</h4>
+<ul>
+<li>Project: Write an algorithm in C/C++; use HLS to make a bit file which can be burned in hardware.</li>
+</ul>
+<p style="text-align: justify;">Additional Read (if time permit) : </p>
+<p style="text-align: justify;">- &nbsp; Computation-centric Algorithms</p>
+<p style="text-align: justify;">- &nbsp; Control centric algorithms</p>
+<p style="text-align: justify;">- &nbsp; Integration of multiple programs</p>

pages/training-modules/uw-gpu.md

@@ -0,0 +1,28 @@
+---
+permalink: /training-modules/uw-gpu.html
+layout: default
+title: GPU training
+---
+
+# GPU training module 
+<p align="justify">
+This training module aims to introduce the students to the concept of hardware accelerators and programming of heterogeneous systems. This training is dedicated to the usage of GPUs by programming in CUDA, and ALPAKA. 
+The duration of this training is 1 semester (14 weeks). The detailed syllabus and series of lectures can be found below.
+</p>
+- [Course syllabus]({{ site.baseurl }}/training-modules/uw-gpu/syllabus)
+- Series of lectures :
+  - [Lecture 1]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week1_Lecture1.pdf) Introduction to hardware accelerators
+  - [Lecture 2]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week1_Lecture2.pdf) The GPU and its applications in HEP
+  - [Lecture 3]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week2_Lecture3.pdf) Introduction to C++ : Core syntax, variables operators, flow control instructions and functions.
+  - [Lecture 4]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week2_Lecture4.pdf) Introduction to C++ : Scopes and namespaces, compound data types and Object Orientation              
+  - [Lecture 5]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week3_Lecture5.pdf) Introduction to CUDA : Nvidia GPU architecture and CUDA core syntax               
+  - [Lecture 6]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week3_Lecture6.pdf) Introduction to CUDA : Memory managments, synchonization and error handling                
+  - [Lecture 7]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week4_Lecture7.pdf) Introduction to CUDA : Coalesced memory access and performance considerations               
+  - [Lecture 8]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week4_Lecture8.pdf) Introduction to CUDA : Shared memory, atomic operations and the default CUDA stream               
+  - [Lecture 9]({{ site.baseurl }}/404.html) CUDA advanced topics : CUDA streams
+  - [Lecture 10]({{ site.baseurl }}/404.html) CUDA advanced topics : C++ standards
+  - [Lecture 11]({{ site.baseurl }}/404.html) Profiling software with Intel OneAPI Toolset Profilers: Vtune and Advisor 
+  - [Lecture 12]({{ site.baseurl }}/404.html) Introduction to Nvidia profiling tools : Nsight system and Nsight compute
+  - [Lecture 13]({{ site.baseurl }}/404.html) CUDA advanced topics : Managed memory
+  - [Lecture 14]({{ site.baseurl }}/404.html) Introduction to Alpaka : Performance portability, Alpaka platforms, devices, queues and events 
+  - [Lecture 15]({{ site.baseurl }}/404.html) Introduction to Alpaka : Memory managment, device functions and kernels, work division