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tt sim on ecpix5
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@sylefeb
sylefeb committed Aug 27, 2024
1 parent 0f265b4 commit 161cf83
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127 changes: 33 additions & 94 deletions frameworks/boards/ecpix5/ecpix5.v
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Expand Up @@ -28,52 +28,39 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

`define ECPIX5 1
`define ECP5 1
`default_nettype none
$$ECPIX5 = 1
$$ECP5 = 1
$$HARDWARE = 1
$$NUM_LEDS = 12
$$color_depth=6
$$color_max =63
// config
$$config['dualport_bram_supported'] = 'yes'
`default_nettype none
// declare package pins (has to match the hardware pin definition)
// pin.NAME = <WIDTH>
$$pin.leds=12
$$pin.uart_rx=1
$$pin.uart_tx=1
$$pin.P0A1=1 pin.P0A2=1 pin.P0A3=1 pin.P0A4=1
$$pin.P0A7=1 pin.P0A8=1 pin.P0A9=1 pin.P0A10=1
$$pin.P1A1=1 pin.P1A2=1 pin.P1A3=1 pin.P1A4=1
$$pin.P1A7=1 pin.P1A8=1 pin.P1A9=1 pin.P1A10=1
$$pin.P2A1=1 pin.P2A2=1 pin.P2A3=1 pin.P2A4=1
$$pin.P2A7=1 pin.P2A8=1 pin.P2A9=1 pin.P2A10=1
// pin groups and renaming
$$pin.video_r = {pin.P0A4,pin.P0A3,pin.P0A2,pin.P0A1,0,0}
$$pin.video_g = {pin.P1A4,pin.P1A3,pin.P1A2,pin.P1A1,0,0}
$$pin.video_b = {pin.P0A10,pin.P0A9,pin.P0A8,pin.P0A7,0,0}
$$pin.video_hs = {pin.P1A7}
$$pin.video_vs = {pin.P1A8}
$$pin.ram_clk = {pin.P2A4} pin.ram_csn = {pin.P2A1}
$$pin.ram_io0 = {pin.P2A2} pin.ram_io1 = {pin.P2A3}
$$pin.ram_io2 = {pin.P2A7} pin.ram_io3 = {pin.P2A8}
$$pin.ram_bank = {pin.P2A10,pin.P2A9}

module top(
// basic
output [11:0] leds,
`ifdef UART
// uart
output uart_rx,
input uart_tx,
`endif
`ifdef VGA
output P0A1, // r0
output P0A2, // r1
output P0A3, // r2
output P0A4, // r3

output P0A7, // b0
output P0A8, // b1
output P0A9, // b2
output P0A10, // b3

output P1A1, // g0
output P1A2, // g1
output P1A3, // g2
output P1A4, // g3

output P1A7, // hs
output P1A8, // vs
`endif
`ifdef PMOD_QQSPI
output P2A1,
inout P2A2,
inout P2A3,
output P2A4,
inout P2A7,
inout P2A8,
output P2A9,
output P2A10,
`endif
%TOP_SIGNATURE%
input clk100
);

Expand All @@ -95,67 +82,19 @@ always @(posedge clk100) begin
end
end

wire [11:0] __main_leds;

`ifdef VGA
wire __main_out_vga_hs;
wire __main_out_vga_vs;
wire __main_out_vga_v0;
wire [5:0] __main_out_vga_r;
wire [5:0] __main_out_vga_g;
wire [5:0] __main_out_vga_b;
`endif

wire run_main;
assign run_main = 1'b1;

M_main __main(
.reset (RST_q[0]),
.in_run (run_main),
.out_leds (__main_leds),
`ifdef UART
.out_uart_tx (uart_rx),
.in_uart_rx (uart_tx),
`endif
`ifdef VGA
.out_video_hs(__main_out_vga_hs),
.out_video_vs(__main_out_vga_vs),
.out_video_r(__main_out_vga_r),
.out_video_g(__main_out_vga_g),
.out_video_b(__main_out_vga_b),
`endif
`ifdef PMOD_QQSPI
.inout_ram_io0(P2A2),
.inout_ram_io1(P2A3),
.inout_ram_io2(P2A7),
.inout_ram_io3(P2A8),
.out_ram_clk(P2A4),
.out_ram_csn(P2A1),
.out_ram_bank({P2A10,P2A9}),
`endif
.clock (clk100)
);
wire design_clk;

assign leds = ~__main_leds;
%WIRE_DECL%

`ifdef VGA
assign P0A1 = __main_out_vga_r[2+:1];
assign P0A2 = __main_out_vga_r[3+:1];
assign P0A3 = __main_out_vga_r[4+:1];
assign P0A4 = __main_out_vga_r[5+:1];

assign P0A7 = __main_out_vga_b[2+:1];
assign P0A8 = __main_out_vga_b[3+:1];
assign P0A9 = __main_out_vga_b[4+:1];
assign P0A10 = __main_out_vga_b[5+:1];

assign P1A1 = __main_out_vga_g[2+:1];
assign P1A2 = __main_out_vga_g[3+:1];
assign P1A3 = __main_out_vga_g[4+:1];
assign P1A4 = __main_out_vga_g[5+:1];

assign P1A7 = __main_out_vga_hs;
assign P1A8 = __main_out_vga_vs;
`endif
M_main __main(
.clock (clk100),
.out_clock(design_clk),
.reset (RST_q[0]),
%MAIN_GLUE%
.in_run (run_main)
);

endmodule
19 changes: 18 additions & 1 deletion frameworks/boards/tinytapeout/board.json
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Expand Up @@ -27,7 +27,24 @@
"framework" : "tt_icebreaker.v",
"command" : "tt_icebreaker.sh",
"description": "Tinytapeout simulation on icebreaker"
}
},
{
"name" : "tt_ecpix5",
"builder" : "edalize",
"framework" : "tt_ecpix5.v",
"description": "Tinytapeout simulation on ecpix5",
"tool" : "trellis",
"tool_options": [
{
"yosys_synth_options": ["-top top -abc9"],
"nextpnr_options": ["--um5g-85k", "--freq 100", "--package CABGA554", "--timing-allow-fail", "--force"],
"pnr": "next"
}
],
"bitstream" : "build.bit",
"constraints": [{"name": "../ecpix5/ecpix5.lpf", "file_type": "LPF"}],
"program": [{"cmd" : "openFPGAloader", "args" : " -b ecpix5 build.bit"}]
}
]
}
]
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153 changes: 153 additions & 0 deletions frameworks/boards/tinytapeout/tt_ecpix5.v
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@@ -0,0 +1,153 @@
/*
Copyright 2019, (C) Sylvain Lefebvre and contributors
List contributors with: git shortlog -n -s -- <filename>
MIT license
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Software, and to permit persons to whom the Software is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
(header_2_M)
*/

// for tinytapeout we target ice40, but then replace SB_IO cells
// by a custom implementation
`define ICE40 1
$$ICE40=1
`define SIM_SB_IO 1
$$SIM_SB_IO=1

`default_nettype none
$$HARDWARE = 1
$$NUM_LEDS = 12
$$color_depth=6
$$color_max =63
// config
$$config['dualport_bram_supported'] = 'yes'
// declare package pins (has to match the hardware pin definition)
// pin.NAME = <WIDTH>
$$pin.leds=12
$$pin.uart_rx=1
$$pin.uart_tx=1
$$pin.P0A1=1 pin.P0A2=1 pin.P0A3=1 pin.P0A4=1
$$pin.P0A7=1 pin.P0A8=1 pin.P0A9=1 pin.P0A10=1
$$pin.P1A1=1 pin.P1A2=1 pin.P1A3=1 pin.P1A4=1
$$pin.P1A7=1 pin.P1A8=1 pin.P1A9=1 pin.P1A10=1
$$pin.P2A1=1 pin.P2A2=1 pin.P2A3=1 pin.P2A4=1
$$pin.P2A7=1 pin.P2A8=1 pin.P2A9=1 pin.P2A10=1
// pin groups and renaming
$$pin.video_r = {pin.P0A4,pin.P0A3,pin.P0A2,pin.P0A1,0,0}
$$pin.video_g = {pin.P1A4,pin.P1A3,pin.P1A2,pin.P1A1,0,0}
$$pin.video_b = {pin.P0A10,pin.P0A9,pin.P0A8,pin.P0A7,0,0}
$$pin.video_hs = {pin.P1A7}
$$pin.video_vs = {pin.P1A8}
$$pin.ram_clk = {pin.P2A4} pin.ram_csn = {pin.P2A1}
$$pin.ram_io0 = {pin.P2A2} pin.ram_io1 = {pin.P2A3}
$$pin.ram_io2 = {pin.P2A7} pin.ram_io3 = {pin.P2A8}
$$pin.ram_bank = {pin.P2A10,pin.P2A9}

// diamond 3.7 accepts this PLL
// diamond 3.8-3.9 is untested
// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
// cause of this could be from wrong CPHASE/FPHASE parameters
module pll
(
input clkin, // 100 MHz, 0 deg
output clkout0, // 25 MHz, 0 deg
output locked
);
(* FREQUENCY_PIN_CLKI="100" *)
(* FREQUENCY_PIN_CLKOP="25" *)
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
.PLLRST_ENA("DISABLED"),
.INTFB_WAKE("DISABLED"),
.STDBY_ENABLE("DISABLED"),
.DPHASE_SOURCE("DISABLED"),
.OUTDIVIDER_MUXA("DIVA"),
.OUTDIVIDER_MUXB("DIVB"),
.OUTDIVIDER_MUXC("DIVC"),
.OUTDIVIDER_MUXD("DIVD"),
.CLKI_DIV(4),
.CLKOP_ENABLE("ENABLED"),
.CLKOP_DIV(24),
.CLKOP_CPHASE(11),
.CLKOP_FPHASE(0),
.FEEDBK_PATH("CLKOP"),
.CLKFB_DIV(1)
) pll_i (
.RST(1'b0),
.STDBY(1'b0),
.CLKI(clkin),
.CLKOP(clkout0),
.CLKFB(clkout0),
.CLKINTFB(),
.PHASESEL0(1'b0),
.PHASESEL1(1'b0),
.PHASEDIR(1'b1),
.PHASESTEP(1'b1),
.PHASELOADREG(1'b1),
.PLLWAKESYNC(1'b0),
.ENCLKOP(1'b0),
.LOCK(locked)
);
endmodule

module top(
%TOP_SIGNATURE%
input clk100
);

reg ready = 0;

reg [31:0] RST_d;
reg [31:0] RST_q;

always @* begin
RST_d = RST_q >> 1;
end

always @(posedge clk25) begin
if (ready) begin
RST_q <= RST_d;
end else begin
ready <= 1;
RST_q <= 32'b111111111111111111111111111111;
end
end

wire run_main;
assign run_main = 1'b1;

wire design_clk;

wire clk25;
pll _pll(.clkin(clk100),.clkout0(clk25));

%WIRE_DECL%

M_main __main(
.clock (clk25),
.out_clock(design_clk),
.reset (RST_q[0]),
%MAIN_GLUE%
.in_run (run_main)
);

endmodule
10 changes: 6 additions & 4 deletions projects/vga_test/vga_test.si
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Original file line number Diff line number Diff line change
Expand Up @@ -3,13 +3,10 @@
// https://github.com/sylefeb/Silice
// @sylefeb 2019

$$VGA_800_600 = 1
$$VGA_800_600 = nil
$$VGA_1024_768 = nil
$$VGA_1920_1080 = nil

// VGA driver
$include('../common/vga.si')

$$if MOJO then
// Clock
import('../common/plls/mojo_100_25.v')
Expand Down Expand Up @@ -50,6 +47,8 @@ import('../common/plls/ulx3s_100_25.v')
$$end

$$if ECPIX5 then
// Select resolution
$$VGA_800_600 = 1
// Clock
$$if VGA_1024_768 then
import('../common/plls/ecpix5_65.v')
Expand All @@ -62,6 +61,9 @@ import('../common/plls/ecpix5_25.v')
$$end
$$end

// VGA driver
$include('../common/vga.si')

$$if HARDWARE then
// Reset
$include('../common/clean_reset.si')
Expand Down

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