RISC-V Simulator

Environment

• Ubuntu 18.04.1 LTS (GNU/Linux 4.15.0-34-generic x86_64)

Prerequisite

• g++ 7.4.0

Processor extension implementation

• RV64IMACFD

Compile

$ make

Block diagram

• Introduce all slave on bus

Slave	Base Address	Size	Read&Write	Cacheable
Boot ROM	0x00000000	4KBytes	Read-Only	Y
SRAM0	0x00010000	64KBytes	Read-Write	Y
SRAM1	0x00010000	64KBytes	Read-Write	Y
DRAM0	0x20000000	2MBytes	Read-Write	Y
DRAM1	0x80000000	2MBytes	Read-Write	Y

• Also you can modify those configuration throgh rewrite main/main.cpp

Usage

• We provide prog0~prog10 test program that you can check processor is correct or not
• You can use makefile to exacute simulator. e.g.

make sim prog=0

Authors

Yu-Tong Shen

tags: RISC-V