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🧪 Shrink bootloader ISA and RAM requirements #1118

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merged 7 commits into from
Dec 12, 2024
Merged

🧪 Shrink bootloader ISA and RAM requirements #1118

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1b577f1
[bootloader] reduce ISA & RAM requirements
stnolting Dec 11, 2024
9c86f9c
[docs] update bootloader constraints
stnolting Dec 11, 2024
c4fc3b5
[rtl] update default bootloader memory image
stnolting Dec 11, 2024
57f7ffa
[rtl] update version ID
stnolting Dec 11, 2024
33393ea
[changelog] add v1.10.7.1
stnolting Dec 11, 2024
f30aadd
[sw] remove bootloader ISA checks / warning
stnolting Dec 12, 2024
34ff788
[docs] booloader: add link to UG
stnolting Dec 12, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 11.12.2024 | 1.10.7.1 | :test_tube: shrink bootloader's minimal ISA (`rv32e`) and RAM (256 bytes) requirements | [#1118](https://github.com/stnolting/neorv32/pull/1118) |
| 10.12.2024 | [**:rocket:1.10.7**](https://github.com/stnolting/neorv32/releases/tag/v1.10.7) | **New release** | |
| 03.12.2024 | 1.10.6.9 | :sparkles: add ONEWIRE command and data FIFO; :warning: rework ONEWIRE interface register layout; :bug: fix regression: busy flag was stuck at zero | [#1113](https://github.com/stnolting/neorv32/pull/1113) |
| 01.12.2024 | 1.10.6.8 | add TWI bus sensing logic | [#1111](https://github.com/stnolting/neorv32/pull/1111) |
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9 changes: 8 additions & 1 deletion docs/datasheet/software_bootloader.adoc
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Expand Up @@ -6,7 +6,14 @@
This section refers to the **default** NEORV32 bootloader. A pre-compiled memory image for the processor-internal
<<_bootloader_rom_bootrom>> is available in the project's +rtl+ folder: `rtl/core/neorv32_bootloader_image.vhd`.
This image is automatically inserted into the boot ROM when synthesizing the processor with the bootloader being
enabled. **Note that the default bootloader image was compiled for a minimal `rv32i` + priv. ISA!**
enabled.

.Minimal RISC-V ISA and Memory Configuration
[NOTE]
The default bootloader image was compiled for a minimal `rv32e_zicsr_zifencei` ISA configuration and only requires a
RAM size of at least 256 bytes. Both constraints ensure that the bootloader can be executed by any actual CPU/processor
configuration. However, the bootloader can recompiled with different capabilities. See the User Guide
https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader for more information.

The NEORV32 bootloader (`sw/bootloader/bootloader.c`) provides an optional built-in firmware that
allows to upload new application executables at _any time_ without the need to re-synthesize the FPGA's bitstream.
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2 changes: 1 addition & 1 deletion docs/userguide/customizing_the_bootloader.adoc
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Expand Up @@ -12,7 +12,7 @@ bootloader ROM) and the processor has to be re-synthesized.

[NOTE]
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Keep in mind that the maximum size for the bootloader is limited to 8kB and it should be compiled using the
minimal base & privileged ISA `rv32i_zicsr_zifencei` only to ensure it can work independently of the actual CPU configuration.
minimal base & privileged ISA `rv32e_zicsr_zifencei` only to ensure it can work with any actual CPU configuration.

.Bootloader configuration parameters
[cols="<2,^1,^2,<6"]
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