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chore: update to STM32_WPAN v1.20.0 #70

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Jul 23, 2024
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4 changes: 2 additions & 2 deletions src/utility/STM32_WPAN/README.md
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

## Source

[STMicroelectronics/STM32CubeWB Release v1.19.0](https://github.com/STMicroelectronics/STM32CubeWB/releases/tag/v1.19.0)
- Application: [BLE_TransparentMode](https://github.com/STMicroelectronics/STM32CubeWB/tree/v1.19.0/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode)
[STMicroelectronics/STM32CubeWB Release v1.20.0](https://github.com/STMicroelectronics/STM32CubeWB/releases/tag/v1.20.0)
- Application: [BLE_TransparentMode](https://github.com/STMicroelectronics/STM32CubeWB/tree/v1.20.0/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_TransparentMode)

4 changes: 2 additions & 2 deletions src/utility/STM32_WPAN/ble_bufsize.h
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*****************************************************************************
* @file ble_bufsize.h
* @author MDG
*
* @brief Definition of BLE stack buffers size
*****************************************************************************
* @attention
Expand Down Expand Up @@ -49,7 +49,7 @@
*/
#define BLE_MEM_BLOCK_SIZE 32

#if (SLAVE_ONLY != 0) ||(BASIC_FEATURES != 0)
#if (SLAVE_ONLY != 0) || (BASIC_FEATURES != 0)
#define BLE_MEM_BLOCK_X_PTX(n_link) 0
#else
#define BLE_MEM_BLOCK_X_PTX(n_link) (n_link)
Expand Down
5 changes: 4 additions & 1 deletion src/utility/STM32_WPAN/shci.h
Original file line number Diff line number Diff line change
Expand Up @@ -882,6 +882,7 @@ extern "C" {
#define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_SRAM (1<<0)
#define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_INTERNAL_FLASH (0<<1)
#define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_SRAM (1<<1)
#define SHCI_C2_CONFIG_CONFIG1_BIT2_SET_EUI64_FORMAT (1<<2)

/**
* EvtMask1
Expand Down Expand Up @@ -1340,7 +1341,9 @@ typedef struct {
* 1 - BLE NVM Data are written in SRAM cache pointed by BleNvmRamAddress
* - bit1 : 0 - THREAD NVM Data data are flushed in internal secure flash
* 1 - THREAD NVM Data are written in SRAM cache pointed by ThreadNvmRamAddress
* - bit2 to bit7 : Unused, shall be set to 0
* - bit2 : 0 - Thread EUI64 is set to new (and current) format
* 1 - Thread EUI64 is set to old format
* - bit3 to bit7 : Unused, shall be set to 0
* uint8_t EvtMask1 :
* When a bit is set to 0, the event is not reported
* bit0 : Asynchronous Event with Sub Evt Code 0x9201 (= SHCI_SUB_EVT_ERROR_NOTIF)
Expand Down