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Update to latest STM32CubeF1 v1.8.5 #2088

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Aug 4, 2023
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Update to latest STM32CubeF1 v1.8.5 #2088

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cbcfa1f
system(F1) update STM32F1xx HAL Drivers to v1.1.9
fpistm Aug 2, 2023
e2f3a29
system(F1): update STM32F1xx CMSIS Drivers to v4.3.4
fpistm Aug 2, 2023
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30 changes: 14 additions & 16 deletions system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral�s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
Expand Down Expand Up @@ -1350,7 +1349,7 @@ typedef struct
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */

/*!< RTC congiguration */
/*!< RTC configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
Expand Down Expand Up @@ -3380,7 +3379,7 @@ typedef struct
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
Expand Down Expand Up @@ -5927,14 +5926,14 @@ typedef struct
#define USBWakeUp_IRQn CEC_IRQn
#define OTG_FS_WKUP_IRQn CEC_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM6_IRQn TIM6_DAC_IRQn


Expand All @@ -5943,14 +5942,14 @@ typedef struct
#define USBWakeUp_IRQHandler CEC_IRQHandler
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM6_IRQHandler TIM6_DAC_IRQHandler


Expand All @@ -5971,4 +5970,3 @@ typedef struct



/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
34 changes: 16 additions & 18 deletions system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral�s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
Expand Down Expand Up @@ -1679,7 +1678,7 @@ typedef struct
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */

/*!< RTC congiguration */
/*!< RTC configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
Expand Down Expand Up @@ -3727,7 +3726,7 @@ typedef struct
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
Expand Down Expand Up @@ -6529,20 +6528,20 @@ typedef struct
#define ADC1_2_IRQn ADC1_IRQn
#define OTG_FS_WKUP_IRQn CEC_IRQn
#define USBWakeUp_IRQn CEC_IRQn
#define TIM8_BRK_IRQn TIM12_IRQn
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
#define TIM8_BRK_IRQn TIM12_IRQn
#define TIM8_UP_IRQn TIM13_IRQn
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
#define TIM8_TRG_COM_IRQn TIM14_IRQn
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
#define TIM6_IRQn TIM6_DAC_IRQn

Expand All @@ -6551,20 +6550,20 @@ typedef struct
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
#define USBWakeUp_IRQHandler CEC_IRQHandler
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
#define TIM8_UP_IRQHandler TIM13_IRQHandler
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM6_IRQHandler TIM6_DAC_IRQHandler

Expand All @@ -6586,4 +6585,3 @@ typedef struct



/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
18 changes: 8 additions & 10 deletions system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral�s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
Expand Down Expand Up @@ -1203,7 +1202,7 @@ typedef struct
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */

/*!< RTC congiguration */
/*!< RTC configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
Expand Down Expand Up @@ -3166,7 +3165,7 @@ typedef struct
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
Expand Down Expand Up @@ -5314,4 +5313,3 @@ typedef struct



/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
18 changes: 8 additions & 10 deletions system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral�s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
Expand Down Expand Up @@ -1248,7 +1247,7 @@ typedef struct
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */

/*!< RTC congiguration */
/*!< RTC configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
Expand Down Expand Up @@ -3228,7 +3227,7 @@ typedef struct
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
Expand Down Expand Up @@ -5445,4 +5444,3 @@ typedef struct



/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
20 changes: 9 additions & 11 deletions system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral�s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
Expand Down Expand Up @@ -1637,7 +1636,7 @@ typedef struct
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */

/*!< RTC congiguration */
/*!< RTC configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
Expand Down Expand Up @@ -3623,7 +3622,7 @@ typedef struct
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
Expand Down Expand Up @@ -5293,7 +5292,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F1 series)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
#define SPI_CRC_ERROR_WORKAROUND_FEATURE
Expand Down Expand Up @@ -6502,4 +6501,3 @@ typedef struct



/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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