Merge pull request #2558 from thernstig/NUCLEO-C071RB

feat: Add variant NUCLEO-C071RB
stm32duino · Nov 14, 2024 · f919d8c · f919d8c
2 parents 4d577b2 + deaab3c
commit f919d8c
Show file tree

Hide file tree

Showing 9 changed files with 810 additions and 1 deletion.
diff --git a/README.md b/README.md
@@ -125,6 +125,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | Status | Device(s) | Name | Release | Notes |
 | :----: | :-------: | ---- | :-----: | :---- |
 | :green_heart: | STM32C031C6 | [Nucleo C031C6](https://www.st.com/en/evaluation-tools/nucleo-c031c6.html) | *2.5.0* |  |
+| :yellow_heart: | STM32C071RB | [Nucleo C071RB](https://www.st.com/en/evaluation-tools/nucleo-c071rb.html) | **2.9.0** |  |
 | :green_heart:  | STM32F030R8 | [Nucleo F030R8](http://www.st.com/en/evaluation-tools/nucleo-f030r8.html) | *0.2.0* |  |
 | :green_heart:  | STM32F070RB | [Nucleo F070RB](http://www.st.com/en/evaluation-tools/nucleo-f070rb.html) | *2.0.0* |  |
 | :green_heart:  | STM32F072RB | [Nucleo F072RB](http://www.st.com/en/evaluation-tools/nucleo-f072rb.html) | *1.9.0* |  |

diff --git a/boards.txt b/boards.txt
@@ -439,6 +439,20 @@ Nucleo_64.menu.pnum.NUCLEO_C031C6.build.st_extra_flags=-D{build.product_line} {b
 Nucleo_64.menu.pnum.NUCLEO_C031C6.openocd.target=stm32c0x
 Nucleo_64.menu.pnum.NUCLEO_C031C6.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C031.svd
 
+# NUCLEO_C071RB board
+Nucleo_64.menu.pnum.NUCLEO_C071RB=Nucleo C071RB
+Nucleo_64.menu.pnum.NUCLEO_C071RB.node="NOD_C071RB"
+Nucleo_64.menu.pnum.NUCLEO_C071RB.upload.maximum_size=131072
+Nucleo_64.menu.pnum.NUCLEO_C071RB.upload.maximum_data_size=24576
+Nucleo_64.menu.pnum.NUCLEO_C071RB.build.mcu=cortex-m0plus
+Nucleo_64.menu.pnum.NUCLEO_C071RB.build.board=NUCLEO_C071RB
+Nucleo_64.menu.pnum.NUCLEO_C071RB.build.series=STM32C0xx
+Nucleo_64.menu.pnum.NUCLEO_C071RB.build.product_line=STM32C071xx
+Nucleo_64.menu.pnum.NUCLEO_C071RB.build.variant=STM32C0xx/C071R(8-B)T
+Nucleo_64.menu.pnum.NUCLEO_C071RB.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
+Nucleo_64.menu.pnum.NUCLEO_C071RB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
+Nucleo_64.menu.pnum.NUCLEO_C071RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd
+
 # NUCLEO_F030R8 board
 Nucleo_64.menu.pnum.NUCLEO_F030R8=Nucleo F030R8
 Nucleo_64.menu.pnum.NUCLEO_F030R8.node="NODE_F030R8,NUCLEO"

diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
@@ -102174,6 +102174,88 @@ target_compile_options(NUCLEO_C031C6_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# NUCLEO_C071RB
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_C071RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C071R(8-B)T")
+set(NUCLEO_C071RB_MAXSIZE 131072)
+set(NUCLEO_C071RB_MAXDATASIZE 24576)
+set(NUCLEO_C071RB_MCU cortex-m0plus)
+set(NUCLEO_C071RB_FPCONF "-")
+add_library(NUCLEO_C071RB INTERFACE)
+target_compile_options(NUCLEO_C071RB INTERFACE
+  "SHELL:-DSTM32C071xx   -D__CORTEX_SC=0"
+  "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${NUCLEO_C071RB_MCU}
+)
+target_compile_definitions(NUCLEO_C071RB INTERFACE
+  "STM32C0xx"
+	"ARDUINO_NUCLEO_C071RB"
+	"BOARD_NAME=\"NUCLEO_C071RB\""
+	"BOARD_ID=NUCLEO_C071RB"
+	"VARIANT_H=\"variant_NUCLEO_C071RB.h\""
+)
+target_include_directories(NUCLEO_C071RB INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${NUCLEO_C071RB_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_C071RB INTERFACE
+  "LINKER:--default-script=${NUCLEO_C071RB_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=131072"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=24576"
+  "SHELL: "
+  -mcpu=${NUCLEO_C071RB_MCU}
+)
+
+add_library(NUCLEO_C071RB_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_C071RB_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_C071RB_serial_generic INTERFACE)
+target_compile_options(NUCLEO_C071RB_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_C071RB_serial_none INTERFACE)
+target_compile_options(NUCLEO_C071RB_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_C071RB_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_C071RB_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_C071RB_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_C071RB_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_C071RB_usb_HID INTERFACE)
+target_compile_options(NUCLEO_C071RB_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_C071RB_usb_none INTERFACE)
+target_compile_options(NUCLEO_C071RB_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_C071RB_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_C071RB_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_C071RB_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_C071RB_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_C071RB_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_C071RB_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # NUCLEO_F030R8
 # -----------------------------------------------------------------------------
 

diff --git a/libraries/USBDevice/inc/usbd_conf.h b/libraries/USBDevice/inc/usbd_conf.h
@@ -74,7 +74,7 @@ extern "C" {
 #elif defined(STM32G0xx)
 #define USB_IRQn USB_UCPD1_2_IRQn
 #define USB_IRQHandler USB_UCPD1_2_IRQHandler
-#elif defined(STM32H5xx) || defined(STM32U0xx)
+#elif defined(STM32C0xx) || defined(STM32H5xx) || defined(STM32U0xx)
 #define USB_IRQn USB_DRD_FS_IRQn
 #define USB_IRQHandler USB_DRD_FS_IRQHandler
 #elif defined(STM32U5xx) && !defined(USB_DRD_FS)

diff --git a/system/STM32C0xx/stm32c0xx_hal_conf_default.h b/system/STM32C0xx/stm32c0xx_hal_conf_default.h
@@ -46,10 +46,12 @@ extern "C" {
 #define HAL_EXTI_MODULE_ENABLED
 #define HAL_FLASH_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
 #define HAL_I2S_MODULE_ENABLED
 #define HAL_IRDA_MODULE_ENABLED
 #define HAL_IWDG_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
 #define HAL_PWR_MODULE_ENABLED
 #define HAL_RCC_MODULE_ENABLED
 #define HAL_RTC_MODULE_ENABLED
@@ -248,6 +250,10 @@ in voltage and temperature.*/
 #include "stm32c0xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
 
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32c0xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
 #ifdef HAL_I2C_MODULE_ENABLED
 #include "stm32c0xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
@@ -264,6 +270,10 @@ in voltage and temperature.*/
 #include "stm32c0xx_hal_iwdg.h"
 #endif /* HAL_IWDG_MODULE_ENABLED */
 
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32c0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
 #ifdef HAL_PWR_MODULE_ENABLED
 #include "stm32c0xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */

diff --git a/variants/STM32C0xx/C071R(8-B)T/CMakeLists.txt b/variants/STM32C0xx/C071R(8-B)T/CMakeLists.txt
@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
 add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
+  PeripheralPins_NUCLEO_C071RB.c
   variant_generic.cpp
+  variant_NUCLEO_C071RB.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)