Merge #411

411: update deps, release 0.9.0 r=therealprof a=burrbull



Co-authored-by: Andrey Zgarbul <[email protected]>

CHANGELOG.md

@@ -7,16 +7,19 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.9.0] - 2022-03-02
+
 ### Added
 
 - Reexport gpio pins to `gpio` mod
 - Added the ability to specify the word size (8 or 9 bits) for `Serial` (USART). When using parity, the parity bit is included in the number of bits of the word.
 - `blocking::serial::Write` for `Tx` and `Serial`. `core::fmt::Write` for `Serial`
 - `Instance` for Timer's, rtic-monotonic fugit impl
-- Serial can now be reconfigured, allowing to change e.g. the baud rate after initialisation.
+- Serial can now be reconfigured, allowing to change e.g. the baud rate after initialization.
 
 ### Changed
 
+- Use `embedded-dma` 0.2.0
 - Connectivity line devices configuration supports ADC2
 - replace `GetBusFreq` with `BusClock` and `BusTimerClock`
 
@@ -302,7 +305,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - First tagged version
 
-[Unreleased]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.8.0...HEAD
+[Unreleased]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.9.0...HEAD
+[v0.9.0]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.8.0...v0.9.0
 [v0.8.0]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.7.0...v0.8.0
 [v0.7.0]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.6.1...v0.7.0
 [v0.6.1]: https://github.com/stm32-rs/stm32f1xx-hal/compare/v0.6.0...v0.6.1

Cargo.toml

@@ -9,21 +9,21 @@ repository = "https://github.com/stm32-rs/stm32f1xx-hal"
 documentation = "https://docs.rs/stm32f1xx-hal"
 readme = "README.md"
 edition = "2018"
-version = "0.8.0"
+version = "0.9.0"
 
 [package.metadata.docs.rs]
 features = ["stm32f103", "rt"]
 default-target = "x86_64-unknown-linux-gnu"
 
 [dependencies]
 cortex-m = "0.7.4"
-cortex-m-rt = "0.7"
+cortex-m-rt = "0.7.1"
 nb = "1"
 stm32f1 = "0.14.0"
-embedded-dma = "0.1.2"
+embedded-dma = "0.2.0"
 bxcan = "0.6"
 void = { default-features = false, version = "1.0.2" }
-embedded-hal = { features = ["unproven"], version = "0.2.6" }
+embedded-hal = { features = ["unproven"], version = "0.2.7" }
 fugit = "0.3.5"
 fugit-timer = "0.1.3"
 rtic-monotonic = { version = "1.0", optional = true }
@@ -39,7 +39,7 @@ panic-semihosting = "0.5.6"
 panic-itm = "0.4.1"
 cortex-m-rtic = "1.0.0"
 cortex-m-semihosting = "0.3.7"
-heapless = "0.7.9"
+heapless = "0.7.10"
 mfrc522 = "0.2.0"
 usb-device = "0.2.8"
 usbd-serial = "0.1.1"

README.md

@@ -186,7 +186,7 @@ be specified as part of the `Cargo.toml` definition.
 
 ```toml
 [dependencies.stm32f1xx-hal]
-version = "0.6.1"
+version = "0.9.0"
 features = ["stm32f100", "rt"]
 ```
 

src/adc.rs

@@ -11,7 +11,7 @@ use crate::rcc::{Clocks, Enable, Reset};
 use crate::time::kHz;
 use core::sync::atomic::{self, Ordering};
 use cortex_m::asm::delay;
-use embedded_dma::StaticWriteBuffer;
+use embedded_dma::WriteBuffer;
 
 use crate::pac::{self, RCC};
 
@@ -735,13 +735,13 @@ macro_rules! adcdma {
  impl<B, PINS, MODE> crate::dma::CircReadDma<B, u16> for AdcDma<$ADCX, PINS, MODE, $dmarxch>
  where
  Self: TransferPayload,
- &'static mut [B; 2]: StaticWriteBuffer<Word = u16>,
+ &'static mut [B; 2]: WriteBuffer<Word = u16>,
  B: 'static,
  {
  fn circ_read(mut self, mut buffer: &'static mut [B; 2]) -> CircBuffer<B, Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (ptr, len) = unsafe { buffer.static_write_buffer() };
+ let (ptr, len) = unsafe { buffer.write_buffer() };
  self.channel.set_peripheral_address(
  unsafe { &(*<$ADCX>::ptr()).dr as *const _ as u32 },
  false,
@@ -775,12 +775,12 @@ macro_rules! adcdma {
  impl<B, PINS, MODE> crate::dma::ReadDma<B, u16> for AdcDma<$ADCX, PINS, MODE, $dmarxch>
  where
  Self: TransferPayload,
- B: StaticWriteBuffer<Word = u16>,
+ B: WriteBuffer<Word = u16>,
  {
  fn read(mut self, mut buffer: B) -> Transfer<W, B, Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (ptr, len) = unsafe { buffer.static_write_buffer() };
+ let (ptr, len) = unsafe { buffer.write_buffer() };
  self.channel.set_peripheral_address(
  unsafe { &(*<$ADCX>::ptr()).dr as *const _ as u32 },
  false,

src/dma.rs

@@ -5,7 +5,7 @@ use core::{
  marker::PhantomData,
  sync::atomic::{compiler_fence, Ordering},
 };
-use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
+use embedded_dma::{ReadBuffer, WriteBuffer};
 
 #[derive(Debug)]
 #[non_exhaustive]
@@ -35,7 +35,7 @@ where
 
 impl<BUFFER, PAYLOAD> CircBuffer<BUFFER, PAYLOAD>
 where
- &'static mut [BUFFER; 2]: StaticWriteBuffer,
+ &'static mut [BUFFER; 2]: WriteBuffer,
  BUFFER: 'static,
 {
  pub(crate) fn new(buf: &'static mut [BUFFER; 2], payload: PAYLOAD) -> Self {
@@ -563,7 +563,7 @@ pub trait Transmit {
 /// Trait for circular DMA readings from peripheral to memory.
 pub trait CircReadDma<B, RS>: Receive
 where
- &'static mut [B; 2]: StaticWriteBuffer<Word = RS>,
+ &'static mut [B; 2]: WriteBuffer<Word = RS>,
  B: 'static,
  Self: core::marker::Sized,
 {
@@ -573,7 +573,7 @@ where
 /// Trait for DMA readings from peripheral to memory.
 pub trait ReadDma<B, RS>: Receive
 where
- B: StaticWriteBuffer<Word = RS>,
+ B: WriteBuffer<Word = RS>,
  Self: core::marker::Sized + TransferPayload,
 {
  fn read(self, buffer: B) -> Transfer<W, B, Self>;
@@ -582,7 +582,7 @@ where
 /// Trait for DMA writing from memory to peripheral.
 pub trait WriteDma<B, TS>: Transmit
 where
- B: StaticReadBuffer<Word = TS>,
+ B: ReadBuffer<Word = TS>,
  Self: core::marker::Sized + TransferPayload,
 {
  fn write(self, buffer: B) -> Transfer<R, B, Self>;
@@ -591,8 +591,8 @@ where
 /// Trait for DMA simultaneously reading and writing within one synchronous operation. Panics if both buffers are not of equal length.
 pub trait ReadWriteDma<RXB, TXB, TS>: Transmit
 where
- RXB: StaticWriteBuffer<Word = TS>,
- TXB: StaticReadBuffer<Word = TS>,
+ RXB: WriteBuffer<Word = TS>,
+ TXB: ReadBuffer<Word = TS>,
  Self: core::marker::Sized + TransferPayload,
 {
  fn read_write(self, rx_buffer: RXB, tx_buffer: TXB) -> Transfer<W, (RXB, TXB), Self>;

src/serial.rs

@@ -83,7 +83,7 @@ use core::convert::Infallible;
 use core::marker::PhantomData;
 use core::ops::Deref;
 use core::sync::atomic::{self, Ordering};
-use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
+use embedded_dma::{ReadBuffer, WriteBuffer};
 use embedded_hal::serial::Write;
 
 use crate::afio::MAPR;
@@ -968,13 +968,13 @@ macro_rules! serialdma {
 
  impl<B> crate::dma::CircReadDma<B, u8> for $rxdma
  where
- &'static mut [B; 2]: StaticWriteBuffer<Word = u8>,
+ &'static mut [B; 2]: WriteBuffer<Word = u8>,
  B: 'static,
  {
  fn circ_read(mut self, mut buffer: &'static mut [B; 2]) -> CircBuffer<B, Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (ptr, len) = unsafe { buffer.static_write_buffer() };
+ let (ptr, len) = unsafe { buffer.write_buffer() };
  self.channel.set_peripheral_address(unsafe{ &(*$USARTX::ptr()).dr as *const _ as u32 }, false);
  self.channel.set_memory_address(ptr as u32, true);
  self.channel.set_transfer_length(len);
@@ -998,12 +998,12 @@ macro_rules! serialdma {
 
  impl<B> crate::dma::ReadDma<B, u8> for $rxdma
  where
- B: StaticWriteBuffer<Word = u8>,
+ B: WriteBuffer<Word = u8>,
  {
  fn read(mut self, mut buffer: B) -> Transfer<W, B, Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (ptr, len) = unsafe { buffer.static_write_buffer() };
+ let (ptr, len) = unsafe { buffer.write_buffer() };
  self.channel.set_peripheral_address(unsafe{ &(*$USARTX::ptr()).dr as *const _ as u32 }, false);
  self.channel.set_memory_address(ptr as u32, true);
  self.channel.set_transfer_length(len);
@@ -1025,12 +1025,12 @@ macro_rules! serialdma {
 
  impl<B> crate::dma::WriteDma<B, u8> for $txdma
  where
- B: StaticReadBuffer<Word = u8>,
+ B: ReadBuffer<Word = u8>,
  {
  fn write(mut self, buffer: B) -> Transfer<R, B, Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (ptr, len) = unsafe { buffer.static_read_buffer() };
+ let (ptr, len) = unsafe { buffer.read_buffer() };
 
  self.channel.set_peripheral_address(unsafe{ &(*$USARTX::ptr()).dr as *const _ as u32 }, false);
 

src/spi.rs

@@ -49,7 +49,7 @@ use crate::rcc::{BusClock, Clocks, Enable, Reset};
 use crate::time::Hertz;
 
 use core::sync::atomic::{self, Ordering};
-use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
+use embedded_dma::{ReadBuffer, WriteBuffer};
 
 /// SPI error
 #[derive(Debug)]
@@ -625,12 +625,12 @@ macro_rules! spi_dma {
 
  impl<B, REMAP, PIN> crate::dma::ReadDma<B, u8> for SpiRxDma<$SPIi, REMAP, PIN, $RCi>
  where
- B: StaticWriteBuffer<Word = u8>,
+ B: WriteBuffer<Word = u8>,
  {
  fn read(mut self, mut buffer: B) -> Transfer<W, B, Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (ptr, len) = unsafe { buffer.static_write_buffer() };
+ let (ptr, len) = unsafe { buffer.write_buffer() };
  self.channel.set_peripheral_address(
  unsafe { &(*<$SPIi>::ptr()).dr as *const _ as u32 },
  false,
@@ -668,12 +668,12 @@ macro_rules! spi_dma {
 
  impl<B, REMAP, PIN> crate::dma::WriteDma<B, u8> for SpiTxDma<$SPIi, REMAP, PIN, $TCi>
  where
- B: StaticReadBuffer<Word = u8>,
+ B: ReadBuffer<Word = u8>,
  {
  fn write(mut self, buffer: B) -> Transfer<R, B, Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (ptr, len) = unsafe { buffer.static_read_buffer() };
+ let (ptr, len) = unsafe { buffer.read_buffer() };
  self.channel.set_peripheral_address(
  unsafe { &(*<$SPIi>::ptr()).dr as *const _ as u32 },
  false,
@@ -712,8 +712,8 @@ macro_rules! spi_dma {
  impl<RXB, TXB, REMAP, PIN> crate::dma::ReadWriteDma<RXB, TXB, u8>
  for SpiRxTxDma<$SPIi, REMAP, PIN, $RCi, $TCi>
  where
- RXB: StaticWriteBuffer<Word = u8>,
- TXB: StaticReadBuffer<Word = u8>,
+ RXB: WriteBuffer<Word = u8>,
+ TXB: ReadBuffer<Word = u8>,
  {
  fn read_write(
  mut self,
@@ -722,8 +722,8 @@ macro_rules! spi_dma {
  ) -> Transfer<W, (RXB, TXB), Self> {
  // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  // until the end of the transfer.
- let (rxptr, rxlen) = unsafe { rxbuffer.static_write_buffer() };
- let (txptr, txlen) = unsafe { txbuffer.static_read_buffer() };
+ let (rxptr, rxlen) = unsafe { rxbuffer.write_buffer() };
+ let (txptr, txlen) = unsafe { txbuffer.read_buffer() };
 
  if rxlen != txlen {
  panic!("receive and send buffer lengths do not match!");