Add support for const variables
#975
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
SystemVerilog allows to declare const variables. These variables are read-only and can not be assigned a value after their declaration. It is only possible to assign an initial value as an initializer. E.g. ``` const int x = 10; x = 20; // Error ``` The LRM requires that for variable declarations with static storage the initializer is a constant expression with the extension that other const variables are also allowed. const variables with automatic storage can be initialized by any expression. Checking if an expression contains only const variables requires a bit more work to implement. So for now be more lenient that what the standard requires and allow arbitrary expressions to initialize const variables even for those with static storage. Signed-off-by: Lars-Peter Clausen <[email protected]>
Check that const variables are supported and they can not be overridden by type of assignment. Signed-off-by: Lars-Peter Clausen <[email protected]>
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
SystemVerilog allows to declare const variables. These variables are
read-only and can not be assigned a value after their declaration. It is
only possible to assign an initial value as an initializer.
E.g.
The LRM requires that for variable declarations with static storage the
initializer is a constant expression with the extension that other const
variables are also allowed. const variables with automatic storage can
be initialized by any expression.
Checking if an expression contains only const variables requires a bit more
work to implement. So for now be more lenient that what the standard
requires and allow arbitrary expressions to initialize const variables even
for those with static storage.