Add testcase with input and output vectors

ivtest/gold/sdf_interconnect4-vvp-stdout.gold

@@ -0,0 +1,10 @@
+time=0 a=xxx b=xxx
+time=5000 a=000 b=xxx
+time=5140 a=000 b=xx0
+time=5160 a=000 b=x00
+time=5200 a=000 b=000
+time=15000 a=111 b=000
+time=15140 a=111 b=001
+time=15160 a=111 b=011
+time=15200 a=111 b=111
+ivltests/sdf_interconnect4.v:58: $finish called at 25000 (1ps)

ivtest/ivltests/sdf_interconnect4.sdf

@@ -0,0 +1,58 @@
+(DELAYFILE
+ (SDFVERSION "3.0")
+ (DESIGN "test")
+ (DATE "Wed Mar 8 12:34:56 2023")
+ (VENDOR "No Vendor")
+ (PROGRAM "Human")
+ (VERSION "1.0.0")
+ (DIVIDER .)
+ (VOLTAGE 5.5:5.0:4.5)
+ (PROCESS "best=0.65:nom=1.0:worst=1.8")
+ (TEMPERATURE -25.0:25.0:85.0)
+ (TIMESCALE 1 ns)
+
+ (CELL
+ (CELLTYPE "my_design")
+ (INSTANCE) 
+ (DELAY
+ (ABSOLUTE
+ (INTERCONNECT a[0] buffer0.in (0.000:0.020:0.000) (0.000:0.020:0.000))
+ (INTERCONNECT buffer0.out b[0] (0.000:0.020:0.000) (0.000:0.020:0.000))
+ (INTERCONNECT a[1] buffer1.in (0.000:0.030:0.000) (0.000:0.030:0.000))
+ (INTERCONNECT buffer1.out b[1] (0.000:0.030:0.000) (0.000:0.030:0.000))
+ (INTERCONNECT a[2] buffer2.in (0.000:0.050:0.000) (0.000:0.050:0.000))
+ (INTERCONNECT buffer2.out b[2] (0.000:0.050:0.000) (0.000:0.050:0.000))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "buffer")
+ (INSTANCE buffer0)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH in out (0.0:0.1:0.0) (0.0:0.1:0.0))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "buffer")
+ (INSTANCE buffer1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH in out (0.0:0.1:0.0) (0.0:0.1:0.0))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "buffer")
+ (INSTANCE buffer2)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH in out (0.0:0.1:0.0) (0.0:0.1:0.0))
+ )
+ )
+ )
+)

ivtest/ivltests/sdf_interconnect4.v

@@ -0,0 +1,67 @@
+`timescale 1ns/1ps
+
+/*
+ This design tests the interconnection delay
+ for three buffers in parallel with input and output vectors
+*/
+
+module buffer (
+ input in,
+ output out
+);
+ specify
+ (in => out) = (0.0:0.0:0.0);
+ endspecify
+
+ assign out = in;
+
+endmodule
+
+module my_design (
+ input [2:0] a,
+ output [2:0] b
+);
+
+ buffer buffer0 (
+ .in (a[0]),
+ .out (b[0])
+ );
+
+ buffer buffer1 (
+ .in (a[1]),
+ .out (b[1])
+ );
+
+ buffer buffer2 (
+ .in (a[2]),
+ .out (b[2])
+ );
+
+endmodule
+
+module top;
+
+ initial begin
+ $sdf_annotate("ivltests/sdf_interconnect4.sdf", my_design_inst);
+ $monitor("time=%0t a=%b b=%b", $realtime, a, b);
+ end
+
+ reg [2:0] a;
+ wire [2:0] b;
+
+ initial begin
+ #5;
+ a <= 3'b000;
+ #10;
+ a <= 3'b111;
+ #10;
+ $finish;
+ end
+
+ my_design my_design_inst (
+ .a (a),
+ .b (b)
+ );
+
+endmodule
+

ivtest/regress-vvp.list

@@ -97,3 +97,4 @@ timing_check_delayed_signals vvp_tests/timing_check_delayed_signals.json
 sdf_interconnect1 vvp_tests/sdf_interconnect1.json
 sdf_interconnect2 vvp_tests/sdf_interconnect2.json
 sdf_interconnect3 vvp_tests/sdf_interconnect3.json
+sdf_interconnect4 vvp_tests/sdf_interconnect4.json

ivtest/vvp_tests/sdf_interconnect4.json

@@ -0,0 +1,6 @@
+{
+ "type" : "normal",
+ "source" : "sdf_interconnect4.v",
+ "iverilog-args" : [ "-Ttyp", "-ginterconnect", "-gspecify" ],
+ "gold" : "sdf_interconnect4"
+}