Updated from TT07 to TT08.

Manual resync with TinyTapeout/tt07-verilog-template and TinyTapeout/tt08-verilog-template.

.github/workflows/docs.yaml

@@ -20,4 +20,4 @@ jobs:
           make verilog
 
       - name: Build docs
-        uses: TinyTapeout/tt-gds-action/docs@tt07
+        uses: TinyTapeout/tt-gds-action/docs@tt08

.github/workflows/fpga.yaml

@@ -20,4 +20,4 @@ jobs:
           make verilog
 
       - name: FPGA bitstream for TT ASIC Sim (ICE40UP5K)
-        uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt07
+        uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt08

.github/workflows/gds.yaml

@@ -20,14 +20,16 @@ jobs:
           make verilog
 
       - name: Build GDS
-        uses: TinyTapeout/tt-gds-action@tt07
+        uses: TinyTapeout/tt-gds-action@tt08
+        with:
+          flow: openlane2
 
   precheck:
     needs: gds
     runs-on: ubuntu-latest
     steps:
       - name: Run Tiny Tapeout Precheck
-        uses: TinyTapeout/tt-gds-action/precheck@tt07
+        uses: TinyTapeout/tt-gds-action/precheck@tt08
 
   gl_test:
     needs: gds
@@ -39,7 +41,7 @@ jobs:
           submodules: recursive
 
       - name: GL test
-        uses: TinyTapeout/tt-gds-action/gl_test@tt07
+        uses: TinyTapeout/tt-gds-action/gl_test@tt08
 
   viewer:
     needs: gds
@@ -48,4 +50,4 @@ jobs:
       pages: write      # to deploy to Pages
       id-token: write   # to verify the deployment originates from an appropriate source
     steps:
-      - uses: TinyTapeout/tt-gds-action/viewer@tt07
+      - uses: TinyTapeout/tt-gds-action/viewer@tt08

.github/workflows/test.yaml

@@ -44,4 +44,4 @@ jobs:
           name: test-vcd
           path: |
             test/tb.vcd
-            test/result.xml
+            test/results.xml

.gitignore

@@ -4,7 +4,8 @@
 *.vcd
 runs
 tt_submission
-src/user_config.tcl
+src/user_config.json
+src/config_merged.json
 src/project.v
 test/sim_build
 test/__pycache__/

src/config.json

@@ -0,0 +1,86 @@
+{
+  "//": "DO NOT EDIT THIS FILE before reading the comments below:",
+
+  "//": "This is the default configuration for Tiny Tapeout projects. It should fit most designs.",
+  "//": "If you change it, please make sure you understand what you are doing. We are not responsible",
+  "//": "if your project fails because of a bad configuration.",
+
+  "//": "!!! DO NOT EDIT THIS FILE unless you know what you are doing !!!",
+
+  "//": "If you get stuck with this config, please open an issue or get in touch via the discord.",
+
+  "//": "Here are some of the variables you may want to change:",
+
+  "//": "PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.",
+  "//": "Users have reported that values up to 0.8 worked well for them.",
+  "PL_TARGET_DENSITY": 0.6,
+
+  "//": "CLOCK_PERIOD - Increase this in case you are getting setup time violations.",
+  "//": "The value is in nanoseconds, so 20ns == 50MHz.",
+  "CLOCK_PERIOD": 20,
+
+  "//": "Hold slack margin - Increase them in case you are getting hold violations.",
+  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.1,
+  "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.05,
+
+  "//": "RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!",
+  "RUN_LINTER": 1,
+  "LINTER_INCLUDE_PDK_MODELS": 1,
+
+  "//": "If you need a custom clock configuration, read the following documentation first:",
+  "//": "https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios",
+  "CLOCK_PORT": "clk",
+
+  "//": "Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html",
+
+  "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
+  "//": "!!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!",
+  "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
+
+  "//": "Save some time",
+  "RUN_KLAYOUT_XOR": 0,
+  "RUN_KLAYOUT_DRC": 0,
+
+  "//": "Don't put clock buffers on the outputs",
+  "PL_RESIZER_BUFFER_OUTPUT_PORTS": 0,
+
+  "//": "Allow use of specific sky130 cells",
+  "SYNTH_READ_BLACKBOX_LIB": 1,
+
+  "//": "Reduce wasted space",
+  "TOP_MARGIN_MULT": 1,
+  "BOTTOM_MARGIN_MULT": 1,
+  "LEFT_MARGIN_MULT": 6,
+  "RIGHT_MARGIN_MULT": 6,
+
+  "//": "Absolute die size",
+  "FP_SIZING": "absolute",
+
+  "PL_BASIC_PLACEMENT": 0,
+  "GRT_ALLOW_CONGESTION": 1,
+
+  "FP_IO_HLENGTH": 2,
+  "FP_IO_VLENGTH": 2,
+
+  "//": "Use alternative efabless decap cells to solve LI density issue",
+  "DECAP_CELL": [
+    "sky130_fd_sc_hd__decap_3",
+    "sky130_fd_sc_hd__decap_4",
+    "sky130_fd_sc_hd__decap_6",
+    "sky130_fd_sc_hd__decap_8",
+    "sky130_ef_sc_hd__decap_12"
+  ],
+
+  "//": "Clock",
+  "RUN_CTS": 1,
+
+  "//": "Don't use power rings or met5 layer",
+  "DESIGN_IS_CORE": 0,
+  "RT_MAX_LAYER": "met4",
+
+  "//": "MAGIC_DEF_LABELS may cause issues with LVS",
+  "MAGIC_DEF_LABELS": 0,
+
+  "//": "Only export pin area in LEF (without any connected nets)",
+  "MAGIC_WRITE_LEF_PINONLY": 1
+}

src/project.tlv

@@ -123,4 +123,6 @@ module m5_user_module_name (
    assign *uio_out = 8'b0;
    assign *uio_oe = 8'b0;
 
+   // List all unused inputs to prevent warnings
+   wire _unused = &{ena, clk, rst_n, 1'b0};
 endmodule

test/test.py

@@ -1,5 +1,5 @@
 # SPDX-FileCopyrightText: © 2024 Tiny Tapeout
-# SPDX-License-Identifier: MIT
+# SPDX-License-Identifier: Apache-2.0
 
 import cocotb
 from cocotb.clock import Clock