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testsuite/gna: add a test for ghdl#2580
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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package StreamPkg is | ||
generic( | ||
type DAT | ||
); | ||
type streamDataArrayType is array (natural range <>) of DAT; | ||
end StreamPkg; | ||
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package body StreamPkg is | ||
end package body StreamPkg; | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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entity StreamRegSlice is | ||
generic ( | ||
type DAT | ||
); | ||
port ( | ||
rxcDat_i : in DAT; | ||
txcDat_o : out DAT | ||
); | ||
end StreamRegSlice; | ||
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architecture rtl of StreamRegSlice is | ||
begin | ||
txcDat_o <= rxcDat_i; | ||
end rtl; | ||
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use std.env.all; | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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entity StreamTb is | ||
generic ( | ||
WIDTH : positive := 8 | ||
); | ||
package StreamPkgDef is new work.StreamPkg generic map (DAT => std_logic_vector(WIDTH-1 downto 0)); | ||
use StreamPkgDef.all; | ||
end StreamTb; | ||
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architecture behavior of StreamTb is | ||
-- subtype DAT is std_logic_vector(WIDTH-1 downto 0); | ||
signal txcDat : DAT; | ||
signal rxcDat : DAT; | ||
begin | ||
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-- DUT instance | ||
dut : entity work.StreamRegSlice | ||
generic map ( | ||
DAT => DAT | ||
) | ||
port map ( | ||
rxcDat_i => txcDat, | ||
txcDat_o => rxcDat | ||
); | ||
-- rxcDat <= txcDat; | ||
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p_test : process | ||
begin | ||
-- end simulation | ||
for i in 0 to 8-1 loop | ||
txcDat <= std_logic_vector(to_unsigned(i, WIDTH)); | ||
wait for 10 ns; | ||
end loop; | ||
report "Simulation end"; | ||
finish; | ||
end process p_test; | ||
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end behavior; |
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