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testsuite/gna: add a test for ghdl#2580
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tgingold committed Jan 12, 2024
1 parent fb25283 commit 6b8a350
Showing 2 changed files with 83 additions and 0 deletions.
78 changes: 78 additions & 0 deletions testsuite/gna/issue2580/streamtb.vhdl
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@@ -0,0 +1,78 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package StreamPkg is
generic(
type DAT
);
type streamDataArrayType is array (natural range <>) of DAT;
end StreamPkg;

package body StreamPkg is
end package body StreamPkg;



library ieee;
use ieee.std_logic_1164.all;

entity StreamRegSlice is
generic (
type DAT
);
port (
rxcDat_i : in DAT;
txcDat_o : out DAT
);
end StreamRegSlice;

architecture rtl of StreamRegSlice is
begin
txcDat_o <= rxcDat_i;
end rtl;


use std.env.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity StreamTb is
generic (
WIDTH : positive := 8
);
package StreamPkgDef is new work.StreamPkg generic map (DAT => std_logic_vector(WIDTH-1 downto 0));
use StreamPkgDef.all;
end StreamTb;

architecture behavior of StreamTb is
-- subtype DAT is std_logic_vector(WIDTH-1 downto 0);
signal txcDat : DAT;
signal rxcDat : DAT;
begin

-- DUT instance
dut : entity work.StreamRegSlice
generic map (
DAT => DAT
)
port map (
rxcDat_i => txcDat,
txcDat_o => rxcDat
);
-- rxcDat <= txcDat;

p_test : process
begin
-- end simulation
for i in 0 to 8-1 loop
txcDat <= std_logic_vector(to_unsigned(i, WIDTH));
wait for 10 ns;
end loop;
report "Simulation end";
finish;
end process p_test;

end behavior;
5 changes: 5 additions & 0 deletions testsuite/gna/issue2580/testsuite.sh
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@@ -10,6 +10,11 @@ elab_simulate test1
analyze test2.vhdl
elab_simulate test2

if ghdl_is_preelaboration; then
analyze streamtb.vhdl
elab_simulate streamtb
fi

clean

echo "Test successful"

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