testsuite/synth: add more sources for verilog generate #16
Job | Run time |
---|---|
4m 19s | |
0s | |
3m 6s | |
10m 0s | |
3m 16s | |
26s | |
26m 17s | |
10m 11s | |
9m 21s | |
17m 29s | |
21m 25s | |
6m 17s | |
6m 33s | |
6m 55s | |
4m 49s | |
7m 31s | |
5m 2s | |
58m 53s | |
2m 2s | |
5m 13s | |
18m 59s | |
6m 38s | |
2m 17s | |
5m 0s | |
22m 9s | |
1m 58s | |
3m 21s | |
8m 59s | |
3m 20s | |
3m 24s | |
1m 25s | |
1m 21s | |
48s | |
34s | |
2m 48s | |
0s | |
2m 20s | |
4h 54m 26s |