Skip to content

Commit

Permalink
Update golden testfiles for Verilog / SV split
Browse files Browse the repository at this point in the history
  • Loading branch information
@stefanlippuner
stefanlippuner committed Nov 13, 2023
1 parent 6e2101b commit b07feb6
Show file tree
Hide file tree
Showing 162 changed files with 15,289 additions and 566 deletions.
12 changes: 6 additions & 6 deletions testfiles/bug-cernbe/repro.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ module example
assign VMEWrDone = wr_ack_int;

// pipelining for wr-in+rd-out
always @(posedge(Clk))
always_ff @(posedge(Clk))
begin
if (!rst_n)
begin
Expand All @@ -63,7 +63,7 @@ module example

// Register regA
assign regA_o = regA_reg;
always @(posedge(Clk))
always_ff @(posedge(Clk))
begin
if (!rst_n)
begin
Expand All @@ -82,22 +82,22 @@ module example

// Interface sm
assign sm_VMEWrData_o = wr_dat_d0;
always @(posedge(Clk))
always_ff @(posedge(Clk))
begin
if (!rst_n)
sm_wt <= 1'b0;
else
sm_wt <= (sm_wt | sm_ws) & ~sm_VMEWrDone_i;
end
assign sm_VMEWrMem_o = sm_ws;
always @(VMEAddr, wr_adr_d0, sm_wt, sm_ws)
always_comb
if ((sm_ws | sm_wt) == 1'b1)
sm_VMEAddr_o <= wr_adr_d0[1:1];
else
sm_VMEAddr_o <= VMEAddr[1:1];

// Process for write requests.
always @(wr_adr_d0, wr_req_d0, regA_wack, sm_VMEWrDone_i)
always_comb
begin
regA_wreq <= 2'b0;
sm_ws <= 1'b0;
Expand Down Expand Up @@ -131,7 +131,7 @@ module example
end

// Process for read requests.
always @(VMEAddr, VMERdMem, regA_reg, sm_VMERdData_i, sm_VMERdDone_i)
always_comb
begin
// By default ack read requests
rd_dat_d0 <= {16{1'bx}};
Expand Down
168 changes: 168 additions & 0 deletions testfiles/bug-cernbe/repro.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,168 @@

module example
(
input wire Clk,
input wire Rst,
input wire [2:1] VMEAddr,
output reg [15:0] VMERdData,
input wire [15:0] VMEWrData,
input wire VMERdMem,
input wire VMEWrMem,
output wire VMERdDone,
output wire VMEWrDone,

// The first register (with some fields)
output wire [31:0] regA_o,

// CERN-BE bus sm
output reg [1:1] sm_VMEAddr_o,
input wire [15:0] sm_VMERdData_i,
output wire [15:0] sm_VMEWrData_o,
output reg sm_VMERdMem_o,
output wire sm_VMEWrMem_o,
input wire sm_VMERdDone_i,
input wire sm_VMEWrDone_i
);
wire rst_n;
reg rd_ack_int;
reg wr_ack_int;
reg [31:0] regA_reg;
reg [1:0] regA_wreq;
reg [1:0] regA_wack;
reg rd_ack_d0;
reg [15:0] rd_dat_d0;
reg wr_req_d0;
reg [2:1] wr_adr_d0;
reg [15:0] wr_dat_d0;
reg sm_ws;
reg sm_wt;
assign rst_n = ~Rst;
assign VMERdDone = rd_ack_int;
assign VMEWrDone = wr_ack_int;

// pipelining for wr-in+rd-out
always @(posedge(Clk))
begin
if (!rst_n)
begin
rd_ack_int <= 1'b0;
VMERdData <= 16'b0000000000000000;
wr_req_d0 <= 1'b0;
wr_adr_d0 <= 2'b00;
wr_dat_d0 <= 16'b0000000000000000;
end
else
begin
rd_ack_int <= rd_ack_d0;
VMERdData <= rd_dat_d0;
wr_req_d0 <= VMEWrMem;
wr_adr_d0 <= VMEAddr;
wr_dat_d0 <= VMEWrData;
end
end

// Register regA
assign regA_o = regA_reg;
always @(posedge(Clk))
begin
if (!rst_n)
begin
regA_reg <= 32'b00000000000000000000000000000000;
regA_wack <= 2'b0;
end
else
begin
if (regA_wreq[0] == 1'b1)
regA_reg[15:0] <= wr_dat_d0;
if (regA_wreq[1] == 1'b1)
regA_reg[31:16] <= wr_dat_d0;
regA_wack <= regA_wreq;
end
end

// Interface sm
assign sm_VMEWrData_o = wr_dat_d0;
always @(posedge(Clk))
begin
if (!rst_n)
sm_wt <= 1'b0;
else
sm_wt <= (sm_wt | sm_ws) & ~sm_VMEWrDone_i;
end
assign sm_VMEWrMem_o = sm_ws;
always @(VMEAddr, wr_adr_d0, sm_wt, sm_ws)
if ((sm_ws | sm_wt) == 1'b1)
sm_VMEAddr_o <= wr_adr_d0[1:1];
else
sm_VMEAddr_o <= VMEAddr[1:1];

// Process for write requests.
always @(wr_adr_d0, wr_req_d0, regA_wack, sm_VMEWrDone_i)
begin
regA_wreq <= 2'b0;
sm_ws <= 1'b0;
case (wr_adr_d0[2:2])
1'b0:
case (wr_adr_d0[1:1])
1'b0:
begin
// Reg regA
regA_wreq[1] <= wr_req_d0;
wr_ack_int <= regA_wack[1];
end
1'b1:
begin
// Reg regA
regA_wreq[0] <= wr_req_d0;
wr_ack_int <= regA_wack[0];
end
default:
wr_ack_int <= wr_req_d0;
endcase
1'b1:
begin
// Submap sm
sm_ws <= wr_req_d0;
wr_ack_int <= sm_VMEWrDone_i;
end
default:
wr_ack_int <= wr_req_d0;
endcase
end

// Process for read requests.
always @(VMEAddr, VMERdMem, regA_reg, sm_VMERdData_i, sm_VMERdDone_i)
begin
// By default ack read requests
rd_dat_d0 <= {16{1'bx}};
sm_VMERdMem_o <= 1'b0;
case (VMEAddr[2:2])
1'b0:
case (VMEAddr[1:1])
1'b0:
begin
// Reg regA
rd_ack_d0 <= VMERdMem;
rd_dat_d0 <= regA_reg[31:16];
end
1'b1:
begin
// Reg regA
rd_ack_d0 <= VMERdMem;
rd_dat_d0 <= regA_reg[15:0];
end
default:
rd_ack_d0 <= VMERdMem;
endcase
1'b1:
begin
// Submap sm
sm_VMERdMem_o <= VMERdMem;
rd_dat_d0 <= sm_VMERdData_i;
rd_ack_d0 <= sm_VMERdDone_i;
end
default:
rd_ack_d0 <= VMERdMem;
endcase
end
endmodule
8 changes: 4 additions & 4 deletions testfiles/bug-cernbe/sub_repro.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ module sub_repro
assign VMEWrDone = wr_ack_int;

// pipelining for wr-in+rd-out
always @(posedge(Clk))
always_ff @(posedge(Clk))
begin
if (!rst_n)
begin
Expand All @@ -55,7 +55,7 @@ module sub_repro

// Register subrA
assign subrA_o = subrA_reg;
always @(posedge(Clk))
always_ff @(posedge(Clk))
begin
if (!rst_n)
begin
Expand All @@ -73,7 +73,7 @@ module sub_repro
// Register subrB

// Process for write requests.
always @(wr_adr_d0, wr_req_d0, subrA_wack)
always_comb
begin
subrA_wreq <= 1'b0;
case (wr_adr_d0[1:1])
Expand All @@ -92,7 +92,7 @@ module sub_repro
end

// Process for read requests.
always @(VMEAddr, VMERdMem, subrA_reg, subrB_i)
always_comb
begin
// By default ack read requests
rd_dat_d0 <= {16{1'bx}};
Expand Down
116 changes: 116 additions & 0 deletions testfiles/bug-cernbe/sub_repro.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,116 @@

module sub_repro
(
input wire Clk,
input wire Rst,
input wire [1:1] VMEAddr,
output reg [15:0] VMERdData,
input wire [15:0] VMEWrData,
input wire VMERdMem,
input wire VMEWrMem,
output wire VMERdDone,
output wire VMEWrDone,

// The first register (with some fields)
output wire [15:0] subrA_o,

// The first register (with some fields)
input wire [15:0] subrB_i
);
wire rst_n;
reg rd_ack_int;
reg wr_ack_int;
reg [15:0] subrA_reg;
reg subrA_wreq;
reg subrA_wack;
reg rd_ack_d0;
reg [15:0] rd_dat_d0;
reg wr_req_d0;
reg [1:1] wr_adr_d0;
reg [15:0] wr_dat_d0;
assign rst_n = ~Rst;
assign VMERdDone = rd_ack_int;
assign VMEWrDone = wr_ack_int;

// pipelining for wr-in+rd-out
always @(posedge(Clk))
begin
if (!rst_n)
begin
rd_ack_int <= 1'b0;
VMERdData <= 16'b0000000000000000;
wr_req_d0 <= 1'b0;
wr_adr_d0 <= 1'b0;
wr_dat_d0 <= 16'b0000000000000000;
end
else
begin
rd_ack_int <= rd_ack_d0;
VMERdData <= rd_dat_d0;
wr_req_d0 <= VMEWrMem;
wr_adr_d0 <= VMEAddr;
wr_dat_d0 <= VMEWrData;
end
end

// Register subrA
assign subrA_o = subrA_reg;
always @(posedge(Clk))
begin
if (!rst_n)
begin
subrA_reg <= 16'b0000000000000000;
subrA_wack <= 1'b0;
end
else
begin
if (subrA_wreq == 1'b1)
subrA_reg <= wr_dat_d0;
subrA_wack <= subrA_wreq;
end
end

// Register subrB

// Process for write requests.
always @(wr_adr_d0, wr_req_d0, subrA_wack)
begin
subrA_wreq <= 1'b0;
case (wr_adr_d0[1:1])
1'b0:
begin
// Reg subrA
subrA_wreq <= wr_req_d0;
wr_ack_int <= subrA_wack;
end
1'b1:
// Reg subrB
wr_ack_int <= wr_req_d0;
default:
wr_ack_int <= wr_req_d0;
endcase
end

// Process for read requests.
always @(VMEAddr, VMERdMem, subrA_reg, subrB_i)
begin
// By default ack read requests
rd_dat_d0 <= {16{1'bx}};
case (VMEAddr[1:1])
1'b0:
begin
// Reg subrA
rd_ack_d0 <= VMERdMem;
rd_dat_d0 <= subrA_reg;
end
1'b1:
begin
// Reg subrB
rd_ack_d0 <= VMERdMem;
rd_dat_d0 <= subrB_i;
end
default:
rd_ack_d0 <= VMERdMem;
endcase
end
endmodule
Loading

0 comments on commit b07feb6

Please sign in to comment.