Update golden RTL files after elaboration-related fixes

testfiles/bug-cernbe/repro.sv

@@ -36,7 +36,7 @@ module example
   reg [15:0] wr_dat_d0;
   reg sm_ws;
   reg sm_wt;
-  assign rst_n = !Rst;
+  assign rst_n = ~Rst;
   assign VMERdDone = rd_ack_int;
   assign VMEWrDone = wr_ack_int;
 
@@ -84,7 +84,7 @@ module example
     if (!rst_n)
       sm_wt <= 1'b0;
     else
-      sm_wt <= (sm_wt | sm_ws) & !sm_VMEWrDone_i;
+      sm_wt <= (sm_wt | sm_ws) & ~sm_VMEWrDone_i;
   end
   assign sm_VMEWrMem_o = sm_ws;
   always @(VMEAddr, wr_adr_d0, sm_wt, sm_ws)

testfiles/bug-cernbe/sub_repro.sv

@@ -28,7 +28,7 @@ module sub_repro
   reg wr_req_d0;
   reg [1:1] wr_adr_d0;
   reg [15:0] wr_dat_d0;
-  assign rst_n = !Rst;
+  assign rst_n = ~Rst;
   assign VMERdDone = rd_ack_int;
   assign VMEWrDone = wr_ack_int;
 

testfiles/bug-empty/noinp.sv

@@ -54,22 +54,22 @@ module noinp
     if (!rst_n_i)
       wb_rip <= 1'b0;
     else
-      wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int;
+      wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int;
   end
-  assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip;
+  assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip;
 
   always @(posedge(clk_i) or negedge(rst_n_i))
   begin
     if (!rst_n_i)
       wb_wip <= 1'b0;
     else
-      wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int;
+      wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int;
   end
-  assign wr_req_int = (wb_en & wb_we_i) & !wb_wip;
+  assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip;
 
   assign ack_int = rd_ack_int | wr_ack_int;
   assign wb_ack_o = ack_int;
-  assign wb_stall_o = !ack_int & wb_en;
+  assign wb_stall_o = ~ack_int & wb_en;
   assign wb_rty_o = 1'b0;
   assign wb_err_o = 1'b0;
 

testfiles/bug-empty/noout.sv

@@ -1,8 +1,8 @@
 interface t_noout_inter;
   logic [31:0] reg0;
   logic [31:0] reg1;
-  modport master(input reg0, reg1, );
-  modport slave(output reg0, reg1, );
+  modport master(input reg0, reg1);
+  modport slave(output reg0, reg1);
 endinterface
 
 
@@ -47,22 +47,22 @@ module noout
     if (!rst_n_i)
       wb_rip <= 1'b0;
     else
-      wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int;
+      wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int;
   end
-  assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip;
+  assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip;
 
   always @(posedge(clk_i) or negedge(rst_n_i))
   begin
     if (!rst_n_i)
       wb_wip <= 1'b0;
     else
-      wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int;
+      wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int;
   end
-  assign wr_req_int = (wb_en & wb_we_i) & !wb_wip;
+  assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip;
 
   assign ack_int = rd_ack_int | wr_ack_int;
   assign wb_ack_o = ack_int;
-  assign wb_stall_o = !ack_int & wb_en;
+  assign wb_stall_o = ~ack_int & wb_en;
   assign wb_rty_o = 1'b0;
   assign wb_err_o = 1'b0;
 

testfiles/bug-gen_wt/m1.sv

@@ -34,7 +34,7 @@ module m1
   reg [2:2] wr_adr_d0;
   reg [31:0] wr_dat_d0;
   reg sm2_ws;
-  assign rst_n = !Rst;
+  assign rst_n = ~Rst;
   assign VMERdDone = rd_ack_int;
   assign VMEWrDone = wr_ack_int;
 

testfiles/bug-memory/mem64ro.sv

@@ -50,8 +50,8 @@ module mem64ro
   reg [9:2] wr_adr_d0;
   reg [31:0] wr_dat_d0;
   reg [31:0] wr_sel_d0;
-  reg [3:0] DdrCapturesIndex_sel_int;
-  reg [3:0] DdrCapturesIndex_sel_int;
+  reg [3:0] DdrCapturesIndex_0_sel_int;
+  reg [3:0] DdrCapturesIndex_1_sel_int;
 
   // WB decode signals
   always @(wb_sel_i)
@@ -68,22 +68,22 @@ module mem64ro
     if (!rst_n_i)
       wb_rip <= 1'b0;
     else
-      wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int;
+      wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int;
   end
-  assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip;
+  assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip;
 
   always @(posedge(clk_i) or negedge(rst_n_i))
   begin
     if (!rst_n_i)
       wb_wip <= 1'b0;
     else
-      wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int;
+      wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int;
   end
-  assign wr_req_int = (wb_en & wb_we_i) & !wb_wip;
+  assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip;
 
   assign ack_int = rd_ack_int | wr_ack_int;
   assign wb_ack_o = ack_int;
-  assign wb_stall_o = !ack_int & wb_en;
+  assign wb_stall_o = ~ack_int & wb_en;
   assign wb_rty_o = 1'b0;
   assign wb_err_o = 1'b0;
 
@@ -135,7 +135,7 @@ module mem64ro
       .clk_a_i(clk_i),
       .clk_b_i(clk_i),
       .addr_a_i(wb_adr_i[8:3]),
-      .bwsel_a_i(DdrCapturesIndex_sel_int),
+      .bwsel_a_i(DdrCapturesIndex_0_sel_int),
       .data_a_i({32{1'bx}}),
       .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato0),
       .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq0),
@@ -150,15 +150,15 @@ module mem64ro
 
   always @(wr_sel_d0)
       begin
-        DdrCapturesIndex_sel_int <= 4'b0;
-        if (!(wr_sel_d0[7:0] == 8'b0))
-          DdrCapturesIndex_sel_int[0] <= 1'b1;
-        if (!(wr_sel_d0[15:8] == 8'b0))
-          DdrCapturesIndex_sel_int[1] <= 1'b1;
-        if (!(wr_sel_d0[23:16] == 8'b0))
-          DdrCapturesIndex_sel_int[2] <= 1'b1;
-        if (!(wr_sel_d0[31:24] == 8'b0))
-          DdrCapturesIndex_sel_int[3] <= 1'b1;
+        DdrCapturesIndex_0_sel_int <= 4'b0;
+        if (~(wr_sel_d0[7:0] == 8'b0))
+          DdrCapturesIndex_0_sel_int[0] <= 1'b1;
+        if (~(wr_sel_d0[15:8] == 8'b0))
+          DdrCapturesIndex_0_sel_int[1] <= 1'b1;
+        if (~(wr_sel_d0[23:16] == 8'b0))
+          DdrCapturesIndex_0_sel_int[2] <= 1'b1;
+        if (~(wr_sel_d0[31:24] == 8'b0))
+          DdrCapturesIndex_0_sel_int[3] <= 1'b1;
       end
   cheby_dpssram #(
       .g_data_width(32),
@@ -171,7 +171,7 @@ module mem64ro
       .clk_a_i(clk_i),
       .clk_b_i(clk_i),
       .addr_a_i(wb_adr_i[8:3]),
-      .bwsel_a_i(DdrCapturesIndex_sel_int),
+      .bwsel_a_i(DdrCapturesIndex_1_sel_int),
       .data_a_i({32{1'bx}}),
       .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato1),
       .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq1),
@@ -186,15 +186,15 @@ module mem64ro
 
   always @(wr_sel_d0)
       begin
-        DdrCapturesIndex_sel_int <= 4'b0;
-        if (!(wr_sel_d0[7:0] == 8'b0))
-          DdrCapturesIndex_sel_int[0] <= 1'b1;
-        if (!(wr_sel_d0[15:8] == 8'b0))
-          DdrCapturesIndex_sel_int[1] <= 1'b1;
-        if (!(wr_sel_d0[23:16] == 8'b0))
-          DdrCapturesIndex_sel_int[2] <= 1'b1;
-        if (!(wr_sel_d0[31:24] == 8'b0))
-          DdrCapturesIndex_sel_int[3] <= 1'b1;
+        DdrCapturesIndex_1_sel_int <= 4'b0;
+        if (~(wr_sel_d0[7:0] == 8'b0))
+          DdrCapturesIndex_1_sel_int[0] <= 1'b1;
+        if (~(wr_sel_d0[15:8] == 8'b0))
+          DdrCapturesIndex_1_sel_int[1] <= 1'b1;
+        if (~(wr_sel_d0[23:16] == 8'b0))
+          DdrCapturesIndex_1_sel_int[2] <= 1'b1;
+        if (~(wr_sel_d0[31:24] == 8'b0))
+          DdrCapturesIndex_1_sel_int[3] <= 1'b1;
       end
   always @(posedge(clk_i) or negedge(rst_n_i))
   begin

testfiles/bug-memory/mem64ro.vhdl

@@ -57,8 +57,8 @@ architecture syn of mem64ro is
   signal wr_adr_d0                      : std_logic_vector(9 downto 2);
   signal wr_dat_d0                      : std_logic_vector(31 downto 0);
   signal wr_sel_d0                      : std_logic_vector(31 downto 0);
-  signal DdrCapturesIndex_sel_int       : std_logic_vector(3 downto 0);
-  signal DdrCapturesIndex_sel_int       : std_logic_vector(3 downto 0);
+  signal DdrCapturesIndex_0_sel_int     : std_logic_vector(3 downto 0);
+  signal DdrCapturesIndex_1_sel_int     : std_logic_vector(3 downto 0);
 begin
 
   -- WB decode signals
@@ -144,7 +144,7 @@ begin
       clk_a_i              => clk_i,
       clk_b_i              => clk_i,
       addr_a_i             => wb_adr_i(8 downto 3),
-      bwsel_a_i            => DdrCapturesIndex_sel_int,
+      bwsel_a_i            => DdrCapturesIndex_0_sel_int,
       data_a_i             => (others => 'X'),
       data_a_o             => DdrCapturesIndex_DdrCaptures_int_dato0,
       rd_a_i               => DdrCapturesIndex_DdrCaptures_rreq0,
@@ -158,18 +158,18 @@ begin
     );
 
   process (wr_sel_d0) begin
-    DdrCapturesIndex_sel_int <= (others => '0');
+    DdrCapturesIndex_0_sel_int <= (others => '0');
     if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(0) <= '1';
+      DdrCapturesIndex_0_sel_int(0) <= '1';
     end if;
     if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(1) <= '1';
+      DdrCapturesIndex_0_sel_int(1) <= '1';
     end if;
     if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(2) <= '1';
+      DdrCapturesIndex_0_sel_int(2) <= '1';
     end if;
     if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(3) <= '1';
+      DdrCapturesIndex_0_sel_int(3) <= '1';
     end if;
   end process;
   DdrCapturesIndex_DdrCaptures_raminst1: cheby_dpssram
@@ -184,7 +184,7 @@ begin
       clk_a_i              => clk_i,
       clk_b_i              => clk_i,
       addr_a_i             => wb_adr_i(8 downto 3),
-      bwsel_a_i            => DdrCapturesIndex_sel_int,
+      bwsel_a_i            => DdrCapturesIndex_1_sel_int,
       data_a_i             => (others => 'X'),
       data_a_o             => DdrCapturesIndex_DdrCaptures_int_dato1,
       rd_a_i               => DdrCapturesIndex_DdrCaptures_rreq1,
@@ -198,18 +198,18 @@ begin
     );
 
   process (wr_sel_d0) begin
-    DdrCapturesIndex_sel_int <= (others => '0');
+    DdrCapturesIndex_1_sel_int <= (others => '0');
     if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(0) <= '1';
+      DdrCapturesIndex_1_sel_int(0) <= '1';
     end if;
     if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(1) <= '1';
+      DdrCapturesIndex_1_sel_int(1) <= '1';
     end if;
     if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(2) <= '1';
+      DdrCapturesIndex_1_sel_int(2) <= '1';
     end if;
     if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then
-      DdrCapturesIndex_sel_int(3) <= '1';
+      DdrCapturesIndex_1_sel_int(3) <= '1';
     end if;
   end process;
   process (clk_i) begin

testfiles/bug-repmem/bran.sv

@@ -215,22 +215,22 @@ module bran_wb
     if (!wb.rst_n)
       wb_rip <= 1'b0;
     else
-      wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int;
+      wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int;
   end
-  assign rd_req_int = (wb_en & !wb.we) & !wb_rip;
+  assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip;
 
   always @(posedge(wb.clk) or negedge(wb.rst_n))
   begin
     if (!wb.rst_n)
       wb_wip <= 1'b0;
     else
-      wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int;
+      wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int;
   end
-  assign wr_req_int = (wb_en & wb.we) & !wb_wip;
+  assign wr_req_int = (wb_en & wb.we) & ~wb_wip;
 
   assign ack_int = rd_ack_int | wr_ack_int;
   assign wb.ack = ack_int;
-  assign wb.stall = !ack_int & wb_en;
+  assign wb.stall = ~ack_int & wb_en;
   assign wb.rty = 1'b0;
   assign wb.err = 1'b0;
 
@@ -503,7 +503,7 @@ module bran_wb
     if (!wb.rst_n)
       RawData0_rack <= 1'b0;
     else
-      RawData0_rack <= RawData0_re & !RawData0_rack;
+      RawData0_rack <= RawData0_re & ~RawData0_rack;
   end
   assign RawData0_addr_o = adr_int[17:2];
 
@@ -513,7 +513,7 @@ module bran_wb
     if (!wb.rst_n)
       RawData1_rack <= 1'b0;
     else
-      RawData1_rack <= RawData1_re & !RawData1_rack;
+      RawData1_rack <= RawData1_re & ~RawData1_rack;
   end
   assign RawData1_addr_o = adr_int[17:2];
 
@@ -523,7 +523,7 @@ module bran_wb
     if (!wb.rst_n)
       RawData2_rack <= 1'b0;
     else
-      RawData2_rack <= RawData2_re & !RawData2_rack;
+      RawData2_rack <= RawData2_re & ~RawData2_rack;
   end
   assign RawData2_addr_o = adr_int[17:2];
 
@@ -533,7 +533,7 @@ module bran_wb
     if (!wb.rst_n)
       RawData3_rack <= 1'b0;
     else
-      RawData3_rack <= RawData3_re & !RawData3_rack;
+      RawData3_rack <= RawData3_re & ~RawData3_rack;
   end
   assign RawData3_addr_o = adr_int[17:2];