adding statistics and simulation links

sstsimulator · Jul 31, 2024 · ce3d362 · ce3d362
1 parent 162957a
commit ce3d362
Showing 1 changed file with 16 additions and 1 deletion.
diff --git a/src/sst/elements/vanadis/examples/vanadis_L1_L2_L3.py b/src/sst/elements/vanadis/examples/vanadis_L1_L2_L3.py
@@ -53,4 +53,19 @@
 memory.addParams({
     "access_time" : "1000ns",
     "mem_size" : "512MiB"
-})
+})
+
+
+
+# Enable statistics
+sst.setStatisticLoadLevel(7)
+sst.setStatisticOutput("sst.statOutputConsole")
+for a in componentlist:
+    sst.enableAllStatisticsForComponentType(a)
+
+
+# Define the simulation links
+link_cpu_cache_link = sst.Link("link_cpu_cache_link")
+link_cpu_cache_link.connect( (iface, "port", "1000ps"), (l1cache, "high_network_0", "1000ps") )
+link_mem_bus_link = sst.Link("link_mem_bus_link")
+link_mem_bus_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") )