Merge pull request #532 from sstsimulator/mh_fixBackendParam

Automatically Merged using develautotester.py
sstsimulator · Dec 8, 2016 · 54d2d87 · 54d2d87
2 parents c1c29fe + 1c56578
commit 54d2d87
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Showing 10 changed files with 17 additions and 14 deletions.
diff --git a/src/sst/elements/memHierarchy/MESICoherenceController.cc b/src/sst/elements/memHierarchy/MESICoherenceController.cc
@@ -693,7 +693,7 @@ CacheAction MESIController::handleFlushLineInvRequest(MemEvent * event, CacheLin
                         cacheLine->setState(IM);
                         return DONE;
                     }
-                } else if (reqEvent->getCmd() == GetXResp) {
+                } else if (reqEvent->getCmd() == GetX) {
                     cacheLine->setState(SM);
                     return STALL; // Waiting for GetXResp
                 }

diff --git a/src/sst/elements/memHierarchy/libmemHierarchy.cc b/src/sst/elements/memHierarchy/libmemHierarchy.cc
@@ -597,7 +597,7 @@ static SubComponent* create_Mem_RequestReorderSimple(Component * comp, Params& p
 
 static const ElementInfoParam requestReorderSimple_params[] = {
     {"verbose",                 "Sets the verbosity of the backend output", "0" },
-    {"max_requests_per_cycle",  "Maximum number of requests to issue per cycle. 0 or negative is unlimited.", "-1"},
+    {"max_issue_per_cycle",  "Maximum number of requests to issue per cycle. 0 or negative is unlimited.", "-1"},
     {"search_window_size",      "Maximum number of request to search each cycle. 0 or negative is unlimited.", "-1"},
     {"backend",                 "Backend memory system", "memHierarchy.simpleDRAM"},
     { NULL, NULL, NULL }
@@ -610,7 +610,7 @@ static SubComponent* create_Mem_RequestReorderRow(Component * comp, Params& para
 
 static const ElementInfoParam requestReorderRow_params[] = {
     {"verbose",                 "Sets the verbosity of the backend output", "0" },
-    {"max_requests_per_cycle",  "Maximum number of requests to issue per cycle. 0 or negative is unlimited.", "-1"},
+    {"max_issue_per_cycle",  "Maximum number of requests to issue per cycle. 0 or negative is unlimited.", "-1"},
     {"banks",                   "Number of banks", "8"},
     {"bank_interleave_granularity", "Granularity of interleaving in bytes (B), generally a cache line. Must be a power of 2.", "64B"},
     {"row_size",                "Size of a row in bytes (B). Must be a power of 2.", "8KiB"},

diff --git a/src/sst/elements/memHierarchy/membackend/memBackend.h b/src/sst/elements/memHierarchy/membackend/memBackend.h
@@ -51,8 +51,9 @@ class MemBackend : public SubComponent {
             output->fatal(CALL_INFO, -1, "MemBackend: clock is not set\n");
         }
 
-        m_maxReqPerCycle = params.find<>("maxReqPerCycle",-1);
-        m_reqWidth = params.find<>("reqWidth",64);
+        m_maxReqPerCycle = params.find<>("max_requests_per_cycle",-1);
+        if (m_maxReqPerCycle == 0) m_maxReqPerCycle = -1;
+        m_reqWidth = params.find<>("request_width",64);
 
         bool found;
         UnitAlgebra backendRamSize = UnitAlgebra(params.find<std::string>("mem_size", "0B", found));

diff --git a/src/sst/elements/memHierarchy/membackend/requestReorderByRow.cc b/src/sst/elements/memHierarchy/membackend/requestReorderByRow.cc
@@ -27,7 +27,8 @@ RequestReorderRow::RequestReorderRow(Component *comp, Params &params) : SimpleMe
     fixupParams( params, "clock", "backend.clock" );
 
     // Get parameters
-    reqsPerCycle = params.find<int>("max_requests_per_cycle", -1);
+    reqsPerCycle = params.find<int>("max_issue_per_cycle", -1);
+
     banks = params.find<unsigned int>("banks", 8);
     UnitAlgebra rowSize(params.find<std::string>("row_size", "8KiB"));
     maxReqsPerRow = params.find<unsigned int>("reorder_limit", 1);    // No re-ordering

diff --git a/src/sst/elements/memHierarchy/membackend/requestReorderSimple.cc b/src/sst/elements/memHierarchy/membackend/requestReorderSimple.cc
@@ -26,7 +26,7 @@ RequestReorderSimple::RequestReorderSimple(Component *comp, Params &params) : Si
 
     fixupParams( params, "clock", "backend.clock" );
 
-    reqsPerCycle = params.find<int>("max_requests_per_cycle", -1);
+    reqsPerCycle = params.find<int>("max_issue_per_cycle", -1);
     searchWindowSize = params.find<int>("search_window_size", -1);
 
     // Create our backend & copy 'mem_size' through for now

diff --git a/src/sst/elements/memHierarchy/memoryController.cc b/src/sst/elements/memHierarchy/memoryController.cc
@@ -55,6 +55,7 @@ MemController::MemController(ComponentId_t id, Params &params) : Component(id),
     fixupParams( params, "backend.", "backendConvertor.backend." );
     fixupParams( params, "clock", "backendConvertor.backend.clock" );
     fixupParams( params, "request_width", "backendConvertor.request_width" );
+    fixupParams( params, "max_requests_per_cycle", "backendConvertor.backend.max_requests_per_cycle" );
 
     // Output for debug
     dbg.init("@t:--->  ", debugLevel, 0, (Output::output_location_t)params.find<int>("debug", 0));

diff --git a/src/sst/elements/memHierarchy/tests/testBackendChaining.py b/src/sst/elements/memHierarchy/tests/testBackendChaining.py
@@ -169,7 +169,7 @@
     "backend" : "memHierarchy.DelayBuffer",
     "backend.request_delay" : "20ns",
     "backend.backend" : "memHierarchy.reorderByRow",
-    "backend.backendmax_requests_per_cycle" : 2,
+    "backend.backend.max_issue_per_cycle" : 2,
     "backend.backend.reorder_limit" : "20",
     "backend.backend.backend" : "memHierarchy.simpleDRAM",
     "backend.backend.backend.tCAS" : 3, # 11@800MHz roughly coverted to 200MHz

diff --git a/src/sst/elements/memHierarchy/tests/testBackendReorderRow.py b/src/sst/elements/memHierarchy/tests/testBackendReorderRow.py
@@ -166,7 +166,7 @@
     "max_requests_per_cycle" : 50,
     "do_not_back" : 1,
     "backend" : "memHierarchy.reorderByRow",
-    "backend.max_requests_per_cycle" : 2,
+    "backend.max_issue_per_cycle" : 2,
     "backend.reorder_limit" : "20",
     "backend.backend" : "memHierarchy.simpleDRAM",
     "backend.backend.tCAS" : 3, # 11@800MHz roughly coverted to 200MHz

diff --git a/src/sst/elements/memHierarchy/tests/testBackendReorderSimple.py b/src/sst/elements/memHierarchy/tests/testBackendReorderSimple.py
@@ -157,7 +157,7 @@
     "max_requests_per_cycle" : 0,
     "do_not_back" : 1,
     "backend" : "memHierarchy.reorderSimple",
-    "backend.max_requests_per_cycle" : 2,
+    "backend.max_issue_per_cycle" : 2,
     "backend.search_window_size" : 5,
     "backend.backend" : "memHierarchy.simpleDRAM",
     "backend.backend.tCAS" : 3, # 11@800MHz roughly coverted to 200MHz

diff --git a/src/sst/elements/memHierarchy/trivialCPU.cc b/src/sst/elements/memHierarchy/trivialCPU.cc
@@ -111,9 +111,9 @@ void trivialCPU::handleEvent(Interfaces::SimpleMem::Request *req)
     } else {
         SimTime_t et = getCurrentSimTime() - i->second;
         requests.erase(i);
-        out.output("%s: Received Request with command %d (response to %" PRIu64 ", addr 0x%" PRIx64 ") [Time: %" PRIu64 "] [%zu outstanding requests]\n",
+        out.output("%s: Received Request with command %d (addr 0x%" PRIx64 ") [Time: %" PRIu64 "] [%zu outstanding requests]\n",
                 getName().c_str(),
-                req->cmd, req->id, req->addr, et,
+                req->cmd, req->addr, et,
                 requests.size());
         num_reads_returned++;
     }
@@ -183,8 +183,8 @@ bool trivialCPU::clockTic( Cycle_t )
 		memory->sendRequest(req);
 		requests[req->id] =  getCurrentSimTime();
 
-		out.output("%s: %d Issued %s%s (%" PRIu64 ") for address 0x%" PRIx64 "\n",
-                        getName().c_str(), numLS, noncacheable ? "Noncacheable " : "" , cmdString.c_str(), req->id, addr);
+		out.output("%s: %d Issued %s%s for address 0x%" PRIx64 "\n",
+                        getName().c_str(), numLS, noncacheable ? "Noncacheable " : "" , cmdString.c_str(), addr);
 		num_reads_issued++;
 
                 numLS--;