Armv7-M: Allow register overlap in ldm + ldrd #153
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slothy/targets/arm_v7m/arch_v7m.py
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| for ldr, reg in zip(ldrs, regs): | ||
| if reg != ptr: | ||
| ldrs_reordered.append(ldr) | ||
| #log(f"inst.args_out == ptr: {reg}") |
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Please remove this comment.
slothy/targets/arm_v7m/arch_v7m.py
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| for ldr, reg in zip(ldrs, regs): | ||
| if reg == ptr: | ||
| ldrs_reordered.append(ldr) | ||
| #log(f"inst.args_out == ptr: {reg}") |
Or simply extend |
mkannwischer
changed the title
| @@ -29,4 +29,7 @@ smlabt r3,r2, r2, r1 | |||
| asrs r3, r3,#1 | |||
| str r3, [r0,#4] // @slothy:writes=a | |||
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| ldrd r2, r3, [r1, #8] | |||
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This does not actually overlap. Please change to
| ldrd r2, r3, [r1, #8] | |
| ldrd r1, r2, [r1, #8] |
| str r4, [r0] // ........................*..... | ||
| asrs r2, r6, #1 // .........................*.... | ||
| str r2, [r0, #4] // .........................*.... // @slothy:writes=a | ||
| ldm r0, {r0,r1,r2,r3} // ..........................*... |
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Your output shows that you have not turned on fusion. So the code you have commited isn't actually used.
You need to add a call to fusion_region into the corresponding example in example.py
| @@ -670,6 +670,7 @@ def core(self,slothy): | |||
| slothy.config.variable_size=True | |||
| slothy.config.inputs_are_outputs = True | |||
| slothy.optimize(start="start", end="end") | |||
| slothy.fusion_region("start", "end", ssa=False) | |||
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You need to put the fusion_region before the optimize, otherwise this does not help SLOTHY find a better solution.
slothy/targets/arm_v7m/arch_v7m.py
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| @@ -1486,7 +1486,7 @@ def make(cls, src): | |||
| obj.increment = None | |||
| obj.pre_index = 0 | |||
| obj.addr = obj.args_in[0] | |||
| obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra | |||
| #obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra | |||
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Please remove those, not comment them out.
Also we need to test if this affects any other examples in SLOTHY.
For that please make sure you have a clean copy of SLOTHY, and then run
python3 example.py --timeout 60 --only-target=slothy.targets.arm_v7m.cortex_m7
This is going to run for a few hours. Then zip up the output files in examples/opt/armv7m and attach them to this PR.
Previously CI would only run if the PR is created by us or if the PR is labeled with needs-ci. This restriction is not needed as we are using Github's runners anyway. This commit enables it for all PRs. It also runs CI on the main branch.
* This commit simplifies the kyber basemul naive implementations to revert modifications to the code originally taken from pqm4 that were only introduced to accomodate for shortcomings of slothy's abilities.
* This commit simplifies the Dilithium iNTT naive implementations to revert modifications to the code originally taken from pqm4 that were only introduced to accomodate for shortcomings of slothy's abilities. * We can also enable the fixup in more cases due to switching of the loop-type + using `before` tag which is done here, too. This aids with performance.
Fixed the splitting of
ldrdandldmwhen the address register and output register overlap inldrd_imm_splitting_cbandldm_interval_splitting_cb.