Merge pull request #189 from slaclab/pre-release

Release Candidate - v1.7.0
slaclab · Mar 14, 2018 · 5fe843f · 5fe843f
2 parents 9745a49 + 12c5f18
commit 5fe843f
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Showing 166 changed files with 1,211 additions and 1,276 deletions.
diff --git a/axi/rtl/AxiDualPortRam.vhd b/axi/rtl/AxiDualPortRam.vhd
@@ -37,9 +37,7 @@ entity AxiDualPortRam is
       COMMON_CLK_G     : boolean                    := false;
       ADDR_WIDTH_G     : integer range 1 to (2**24) := 5;
       DATA_WIDTH_G     : integer                    := 32;
-      INIT_G           : slv                        := "0";
-      AXI_ERROR_RESP_G : slv(1 downto 0)            := AXI_RESP_DECERR_C);
-
+      INIT_G           : slv                        := "0");
    port (
       -- Axi Port
       axiClk         : in  sl;

diff --git a/axi/rtl/AxiLiteEmptyVector.vhd b/axi/rtl/AxiLiteEmptyVector.vhd
diff --git a/axi/rtl/AxiLiteEmpty.vhd → axi/rtl/AxiLiteRegs.vhd b/axi/rtl/AxiLiteEmpty.vhd → axi/rtl/AxiLiteRegs.vhd
@@ -1,12 +1,6 @@
 -------------------------------------------------------------------------------
--- Title         : AXI Lite Empty End Point
--- File          : AxiLiteEmpty.vhd
--- Author        : Ryan Herbst, [email protected]
--- Created       : 03/10/2014
--------------------------------------------------------------------------------
 -- Description:
--- Empty slave endpoint for AXI Lite bus.
--- Absorbs writes and returns zeros on reads.
+-- Generic register slave endpoint on AXI-Lite bus
 -- Supports a configurable number of write and read vectors.
 -------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
@@ -17,9 +11,6 @@
 -- may be copied, modified, propagated, or distributed except according to 
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------
--- Modification history:
--- 03/10/2014: created.
--------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -29,10 +20,9 @@ use ieee.std_logic_unsigned.all;
 use work.StdRtlPkg.all;
 use work.AxiLitePkg.all;
 
-entity AxiLiteEmpty is
+entity AxiLiteRegs is
    generic (
       TPD_G            : time                  := 1 ns;
-      AXI_ERROR_RESP_G : slv(1 downto 0)       := AXI_RESP_OK_C;
       NUM_WRITE_REG_G  : integer range 1 to 32 := 1;
       NUM_READ_REG_G   : integer range 1 to 32 := 1);
    port (
@@ -46,9 +36,9 @@ entity AxiLiteEmpty is
       -- User Read/Write registers
       writeRegister  : out Slv32Array(NUM_WRITE_REG_G-1 downto 0);
       readRegister   : in  Slv32Array(NUM_READ_REG_G-1 downto 0) := (others => (others => '0')));
-end AxiLiteEmpty;
+end AxiLiteRegs;
 
-architecture rtl of AxiLiteEmpty is
+architecture rtl of AxiLiteRegs is
 
    type RegType is record
       writeRegister : Slv32Array(NUM_WRITE_REG_G-1 downto 0);
@@ -88,7 +78,7 @@ begin
       end loop;
 
       -- Closeout the transaction
-      axiSlaveDefault(regCon, v.axiWriteSlave, v.axiReadSlave, AXI_ERROR_RESP_G);
+      axiSlaveDefault(regCon, v.axiWriteSlave, v.axiReadSlave, AXI_RESP_DECERR_C);
 
       -- Synchronous Reset
       if (axiClkRst = '1') then

diff --git a/axi/rtl/AxiLiteRingBuffer.vhd b/axi/rtl/AxiLiteRingBuffer.vhd
@@ -2,7 +2,7 @@
 -- File       : AxiLiteRingBuffer.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2014-05-02
--- Last update: 2016-02-05
+-- Last update: 2018-01-08
 -------------------------------------------------------------------------------
 -- Description: Wrapper for simple BRAM based ring buffer with AXI-Lite interface
 -------------------------------------------------------------------------------
@@ -30,8 +30,7 @@ entity AxiLiteRingBuffer is
       BRAM_EN_G        : boolean                := true;
       REG_EN_G         : boolean                := true;
       DATA_WIDTH_G     : positive range 1 to 32 := 32;
-      RAM_ADDR_WIDTH_G : positive range 1 to 19 := 10;
-      AXI_ERROR_RESP_G : slv(1 downto 0)        := AXI_RESP_DECERR_C);
+      RAM_ADDR_WIDTH_G : positive range 1 to 19 := 10);
    port (
       -- Data to store in ring buffer
       dataClk         : in  sl;
@@ -276,14 +275,14 @@ begin
       -- Check for write request
       if (axilStatus.writeEnable = '1') then
          -- Check for an out of 32 bit aligned address
-         axiWriteResp := ite(axilWriteMaster.awaddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_ERROR_RESP_G);
+         axiWriteResp := ite(axilWriteMaster.awaddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C);
          -- Check for first mapped address access (which is the control register)
          if (axilWriteMaster.awaddr(RAM_ADDR_WIDTH_G+2-1 downto 2) = 0) then
             v.bufferEnable := axilWriteMaster.wdata(31);
             v.bufferClear  := axilWriteMaster.wdata(30);
          else
             -- Unmapped write register access
-            axiWriteResp := AXI_ERROR_RESP_G;
+            axiWriteResp := AXI_RESP_DECERR_C;
          end if;
          -- Set the Slave's response
          axiSlaveWriteResponse(v.axilWriteSlave, axiWriteResp);
@@ -294,7 +293,7 @@ begin
          -- Reset the read data bus
          v.axilReadSlave.rdata := (others => '0');
          -- Check for an out of 32 bit aligned address
-         axiReadResp           := ite(axilReadMaster.araddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_ERROR_RESP_G);
+         axiReadResp           := ite(axilReadMaster.araddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C);
          -- Control register mapped at address 0
          if (axilReadMaster.araddr(RAM_ADDR_WIDTH_G+2-1 downto 2) = 0) then
             v.axilReadSlave.rdata(31)                          := axilR.bufferEnable;

diff --git a/axi/rtl/AxiLiteToDrp.vhd b/axi/rtl/AxiLiteToDrp.vhd
@@ -2,7 +2,7 @@
 -- File       : AxiLiteToDrp.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2016-02-10
--- Last update: 2016-02-17
+-- Last update: 2018-01-08
 -------------------------------------------------------------------------------
 -- Description: AXI-Lite to Xilinx DRP Bridge 
 -------------------------------------------------------------------------------
@@ -26,7 +26,6 @@ use work.AxiLitePkg.all;
 entity AxiLiteToDrp is
    generic (
       TPD_G            : time                   := 1 ns;
-      AXI_ERROR_RESP_G : slv(1 downto 0)        := AXI_RESP_DECERR_C;
       COMMON_CLK_G     : boolean                := false;
       EN_ARBITRATION_G : boolean                := false;
       TIMEOUT_G        : positive               := 4096;
@@ -234,8 +233,8 @@ begin
                   -- Return good transaction
                   axiResp := AXI_RESP_OK_C;
                else
-                  -- Return good transaction
-                  axiResp     := AXI_ERROR_RESP_G;
+                  -- Return bad transaction
+                  axiResp     := AXI_RESP_SLVERR_C;
                   -- Attempt to re-initialize the DRP interface
                   v.drpUsrRst := '1';
                end if;

diff --git a/axi/rtl/AxiLiteWriteFilter.vhd b/axi/rtl/AxiLiteWriteFilter.vhd
@@ -2,7 +2,7 @@
 -- File       : AxiLiteWriteFilter.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2017-11-13
--- Last update: 2017-11-14
+-- Last update: 2018-01-08
 -------------------------------------------------------------------------------
 -- Description: Module for filtering write access
 -------------------------------------------------------------------------------
@@ -27,8 +27,7 @@ entity AxiLiteWriteFilter is
    generic (
       TPD_G            : time            := 1 ns;
       FILTER_SIZE_G    : positive        := 1;  -- Number of filter addresses
-      FILTER_ADDR_G    : Slv32Array      := (0 => x"00000000");  -- Filter addresses that will be allowed through
-      AXI_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_DECERR_C);
+      FILTER_ADDR_G    : Slv32Array      := (0 => x"00000000"));  -- Filter addresses that will be allowed through
    port (
       -- Clock and reset
       axilClk          : in  sl;
@@ -117,7 +116,7 @@ begin
                if (blockAll = '1') then
                   -- Forward the error message
                   v.sAxilWriteSlave.bvalid := '1';
-                  v.sAxilWriteSlave.bresp  := AXI_ERROR_RESP_G;
+                  v.sAxilWriteSlave.bresp  := AXI_RESP_SLVERR_C;
                   -- Next state
                   v.state                  := BUS_RESP_S;
                elsif (enFilter = '1') then
@@ -155,7 +154,7 @@ begin
             if (r.validAddress = '0') then
                -- Forward the error message
                v.sAxilWriteSlave.bvalid := '1';
-               v.sAxilWriteSlave.bresp  := AXI_ERROR_RESP_G;
+               v.sAxilWriteSlave.bresp  := AXI_RESP_DECERR_C;
                -- Next state
                v.state                  := BUS_RESP_S;
             else

diff --git a/axi/rtl/AxiMemTester.vhd b/axi/rtl/AxiMemTester.vhd
@@ -2,7 +2,7 @@
 -- File       : AxiMemTester.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2015-07-28
--- Last update: 2017-08-14
+-- Last update: 2018-01-08
 -------------------------------------------------------------------------------
 -- Description: General Purpose AXI4 memory tester
 -------------------------------------------------------------------------------
@@ -27,7 +27,6 @@ use work.AxiPkg.all;
 entity AxiMemTester is
    generic (
       TPD_G            : time                     := 1 ns;
-      AXI_ERROR_RESP_G : slv(1 downto 0)          := AXI_RESP_DECERR_C;
       START_ADDR_G     : slv                      := X"00000000";
       STOP_ADDR_G      : slv                      := X"FFFFFFFF";
       BURST_LEN_G      : positive range 1 to 4096 := 4096;
@@ -429,7 +428,7 @@ begin
       axiSlaveRegisterR(regCon, x"128", 0, toSlv(AXI_CONFIG_G.ID_BITS_C, 32));
 
       -- Closeout the transaction
-      axiSlaveDefault(regCon, v.axilWriteSlave, v.axilReadSlave, AXI_ERROR_RESP_G);
+      axiSlaveDefault(regCon, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C);
 
       -- Latch the values from Synchronizers
       v.memReady := done;