Program ISSI QSPI flash for use with Arria 10, Cyclone 10 GX and Cyclone V devices
Quartus 18.1 Prime Lite or Prime Standard
Tested on the Arrow SoCKit board (Cyclone V) and Intel PSG Arria 10 SoC Development kit (Arria 10) using IS25WP512 devices.
For any targets other than the Arrow SoCKit board do the following
- open Quartus 18.1
- change the device to match the target board
- modify the design to match the target board clk input a. identify the clk input pin, io standard and frequency b. modify the assignments for clk input pin and io standard c. modify the sdc file "create_clock" parameter to match the clock period
- open platform designer with the qsys_top.qsys file a. edit the ext_clk_50m component "clock frequency" b. if target is Arria 10 then replace the Altera PLL with the IOPLL component reconnect all clock to the IOPLL component. c. generate the system d. in Quartus under Project --> Add/Remove files in project remove qsys_top/qsys_top.qip and replace with the newly generated one e. compile the design.
- open the utility - Files --> Convert Programming Files a. Programming file type : jic deselect Create Memory Map select Create config data RPD b. output_files/output_file.jic b. Configuration device: 1. Cyclone: Select QSPI128 or QSPI512 (for 3 byte or 4 byte addressing respectively) 2. Arria 10: Select EPCQL512 c. Mode: Active Serial x4 d. Options/Boot info: Select Big Endian e. Advanced: 1. Select Disable EPCS/EPCQ ID check (must see a check mark in the box) 2. QSPI Flash single IO mode dummy clock i. Cyclone: 8 ii. Arria 10: Unchangeable 3. QSPI Flash quad IO mode dummy clock i. Cyclone: 6 ii. Arria 10: Unchangeable f. Input files to convert 1. Flash Loader: Add Device 2. SOF Data: Add File - select the payload sof file 3. Optional: turn on compression - click on sof file - click Properties - select Compression g. Generate h. rename outfile_file_auto.rpd to payload.rpd in output_files folder
This only needs to be done once for a device.
- in the Nios II Command Shell cd to the scripts directory
- For Cyclone V: ./setup_issi_cv.sh
- For Arria 10: ./setup_issi_a10.sh
- connect the usb cable to the target and power on the target board
- in the Nios II Command Shell cd to the scripts directory
- ./program.sh
- ./verify.sh
- power cycle the board
- see if the config done led is illuminated - this indicates the fpga is configured