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arm: Add neon2rvv support in vand series intrinsics
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@howjmay @mr-c
howjmay authored and mr-c committed Apr 21, 2024
1 parent 2a548e5 commit dac67f3
Showing 1 changed file with 32 additions and 0 deletions.
32 changes: 32 additions & 0 deletions simde/arm/neon/and.h
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,8 @@ simde_vand_s8(simde_int8x8_t a, simde_int8x8_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_i8m1(a_.sv64, b_.sv64, 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -77,6 +79,8 @@ simde_vand_s16(simde_int16x4_t a, simde_int16x4_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_i16m1(a_.sv64, b_.sv64, 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -107,6 +111,8 @@ simde_vand_s32(simde_int32x2_t a, simde_int32x2_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_i32m1(a_.sv64, b_.sv64, 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -137,6 +143,8 @@ simde_vand_s64(simde_int64x1_t a, simde_int64x1_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_i64m1(a_.sv64, b_.sv64, 1);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -167,6 +175,8 @@ simde_vand_u8(simde_uint8x8_t a, simde_uint8x8_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_u8m1(a_.sv64, b_.sv64, 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -197,6 +207,8 @@ simde_vand_u16(simde_uint16x4_t a, simde_uint16x4_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_u16m1(a_.sv64, b_.sv64, 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -227,6 +239,8 @@ simde_vand_u32(simde_uint32x2_t a, simde_uint32x2_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_u32m1(a_.sv64, b_.sv64, 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -257,6 +271,8 @@ simde_vand_u64(simde_uint64x1_t a, simde_uint64x1_t b) {

#if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_and_si64(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vand_vv_u64m1(a_.sv64, b_.sv64, 1);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -291,6 +307,8 @@ simde_vandq_s8(simde_int8x16_t a, simde_int8x16_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_i8m1(a_.sv128, b_.sv128, 16);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -325,6 +343,8 @@ simde_vandq_s16(simde_int16x8_t a, simde_int16x8_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_i16m1(a_.sv128, b_.sv128, 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -359,6 +379,8 @@ simde_vandq_s32(simde_int32x4_t a, simde_int32x4_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_i32m1(a_.sv128, b_.sv128, 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -393,6 +415,8 @@ simde_vandq_s64(simde_int64x2_t a, simde_int64x2_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_i64m1(a_.sv128, b_.sv128, 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -427,6 +451,8 @@ simde_vandq_u8(simde_uint8x16_t a, simde_uint8x16_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_u8m1(a_.sv128, b_.sv128, 16);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -461,6 +487,8 @@ simde_vandq_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_u16m1(a_.sv128, b_.sv128, 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -495,6 +523,8 @@ simde_vandq_u32(simde_uint32x4_t a, simde_uint32x4_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_u32m1(a_.sv128, b_.sv128, 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down Expand Up @@ -529,6 +559,8 @@ simde_vandq_u64(simde_uint64x2_t a, simde_uint64x2_t b) {
r_.m128i = _mm_and_si128(a_.m128i, b_.m128i);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_and(a_.v128, b_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vand_vv_u64m1(a_.sv128, b_.sv128, 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = a_.values & b_.values;
#else
Expand Down

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