Add V_CVT_PK_U8_F32 opcode (#1022)

shadps4-emu · Sep 22, 2024 · 8811cc5 · 8811cc5
1 parent 5db2710
commit 8811cc5
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Showing 2 changed files with 13 additions and 0 deletions.
diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h
@@ -216,6 +216,7 @@ class Translator {
     void V_MED3_I32(const GcnInst& inst);
     void V_SAD(const GcnInst& inst);
     void V_SAD_U32(const GcnInst& inst);
+    void V_CVT_PK_U8_F32(const GcnInst& inst);
     void V_LSHL_B64(const GcnInst& inst);
     void V_MUL_F64(const GcnInst& inst);
     void V_MAX_F64(const GcnInst& inst);

diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp
@@ -335,6 +335,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
         return V_MED3_I32(inst);
     case Opcode::V_SAD_U32:
         return V_SAD_U32(inst);
+    case Opcode::V_CVT_PK_U8_F32:
+        return V_CVT_PK_U8_F32(inst);
     case Opcode::V_LSHL_B64:
         return V_LSHL_B64(inst);
     case Opcode::V_MUL_F64:
@@ -1031,6 +1033,16 @@ void Translator::V_SAD_U32(const GcnInst& inst) {
     SetDst(inst.dst[0], ir.IAdd(result, src2));
 }
 
+void Translator::V_CVT_PK_U8_F32(const GcnInst& inst) {
+    const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
+    const IR::U32 src1{GetSrc(inst.src[1])};
+    const IR::U32 src2{GetSrc(inst.src[2])};
+
+    const IR::U32 value_uint = ir.ConvertFToU(32, src0);
+    const IR::U32 offset = ir.ShiftLeftLogical(src1, ir.Imm32(3));
+    SetDst(inst.dst[0], ir.BitFieldInsert(src2, value_uint, offset, ir.Imm32(8)));
+}
+
 void Translator::V_LSHL_B64(const GcnInst& inst) {
     const IR::U64 src0{GetSrc64(inst.src[0])};
     const IR::U64 src1{GetSrc64(inst.src[1])};