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@@ -1,22 +1,41 @@ | ||
from distutils.core import setup | ||
from setuptools import setup | ||
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name = 'svreal' | ||
version = '0.1.3' | ||
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DESCRIPTION = '''\ | ||
Library for working with fixed-point numbers in SystemVerilog\ | ||
''' | ||
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with open('README.md', 'r') as fh: | ||
LONG_DESCRIPTION = fh.read() | ||
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setup( | ||
name='svreal', | ||
version='0.1.2', | ||
name=name, | ||
version=version, | ||
description=DESCRIPTION, | ||
long_description=LONG_DESCRIPTION, | ||
long_description_content_type='text/markdown', | ||
keywords = ['fixed-point', 'fixed point', 'verilog', 'system-verilog', 'system verilog', 'synthesizable', 'fpga'], | ||
packages=[ | ||
f'{name}' | ||
], | ||
scripts=[ | ||
], | ||
install_requires=[ | ||
] | ||
license='MIT', | ||
description='Library for working with fixed-point numbers in SystemVerilog', | ||
url=f'https://github.com/sgherbst/{name}', | ||
author='Steven Herbst', | ||
author_email='[email protected]', | ||
url='https://github.com/sgherbst/svreal', | ||
download_url = 'https://github.com/sgherbst/svreal/archive/v0.1.2.tar.gz', | ||
keywords = ['fixed-point', 'fixed point', 'verilog', 'system-verilog', 'system verilog', 'synthesizable', 'fpga'], | ||
python_requires='>=3.7', | ||
download_url = f'https://github.com/sgherbst/{name}/archive/v{version}.tar.gz', | ||
classifiers=[ | ||
'Development Status :: 3 - Alpha', | ||
'Intended Audience :: Developers', | ||
'Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)', | ||
'License :: OSI Approved :: MIT License', | ||
'Programming Language :: Python :: 3', | ||
'Programming Language :: Python :: 3.7' | ||
f'Programming Language :: Python :: 3.7' | ||
], | ||
zip_safe=False | ||
) |