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Add test for AArch64 cache instructions #97

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Add test for AArch64 cache instructions #97

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Add test for AArch64 cache instructions
Ivan-Velickovic Jul 24, 2023
0f4b23d
Merge branch 'master' into arm_cache_ops_user_space
lsf37 Jun 16, 2024
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49 changes: 49 additions & 0 deletions apps/sel4test-tests/src/tests/cache.c
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Original file line number Diff line number Diff line change
Expand Up @@ -327,3 +327,52 @@ static int test_page_uncached_after_retype(env_t env)
DEFINE_TEST(CACHEFLUSH0004, "Test that mapping a frame uncached doesn't see stale data after retype",
test_page_uncached_after_retype,
config_set(CONFIG_HAVE_CACHE))

/*
* On AArch64, the kernel can allow the user to perform certain cache
* maintenance operations directly, without going into the kernel. The specific
* instructions are DC CVAU, DC CIVAC, DC CVAC, and IC IVAU.
*
* This test ensures that no exceptions arise from executing these instructions
* when the kernel is configured to allow them from user-space.
*
*/
static int test_user_cache_ops(env_t env)
{
seL4_CPtr frame;
uintptr_t vstart;
vka_t *vka;
int err;

vka = &env->vka;

void *vaddr;
reservation_t reservation;

reservation = vspace_reserve_range(&env->vspace,
PAGE_SIZE_4K, seL4_AllRights, 1, &vaddr);
assert(reservation.res);

vstart = (uintptr_t)vaddr;
assert(IS_ALIGNED(vstart, seL4_PageBits));

/* Create a frame */
frame = vka_alloc_frame_leaky(vka, PAGE_BITS_4K);
test_assert(frame != seL4_CapNull);

/* map in a cap with cacheability */
err = vspace_map_pages_at_vaddr(&env->vspace, &frame, NULL, vaddr, 1, seL4_PageBits, reservation);
test_error_eq(err, seL4_NoError);

/* Now that we have a page of memory in our virtual address space, we can
* test the cache instructions in its virtual address. */
asm volatile("dc cvau, %0" :: "r"(vaddr));
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@Ivan-Velickovic Ivan-Velickovic Jul 24, 2023 •
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I'm not super familiar with the sel4test infrastructure, is this the correct way to do this or should I be creating helper threads that execute the instructions and then calling wait_for_helper? If these instructions fail will it crash the whole sel4test run or will just this test fail?

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Using a helper thread would be better IMO as it would allow you to catch the fault in the case where the user mode instructions were not enabled. The way it is currently the test thread would fault and you can't tell whether the failure was due to the code-under-test or the test itself. An inverse of the test would be to check that the instructions trigger an seL4_UserException fault if executed when the config option is not enabled.

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Okay cool I'll do it with a helper thread then. Not sure if you saw my comment in the PR description but is there much point in adding the inverse test since it will never be triggered by CI?

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You could write the test in a way that it unconditionally runs and just checks that the thread result matches the configuration. You could validate that the test passes for both configurations, and CI will test what ever configurations it tests, but because there's only one test implemented it's less likely to go stale for the other configuration but people can still run sel4test on their specific configuration even if the CI doesn't test it.

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@Ivan-Velickovic Ivan-Velickovic Jul 24, 2023 •
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Sure thing, I'll add that then.

asm volatile("dc civac, %0" :: "r"(vaddr));
asm volatile("dc cvac, %0" :: "r"(vaddr));
asm volatile("ic ivau, %0" :: "r"(vaddr));

return sel4test_get_result();
}
DEFINE_TEST(CACHEOPS0001, "Test cache-maintenance instructions from user-space",
test_user_cache_ops,
config_set(CONFIG_HAVE_CACHE) && config_set(CONFIG_AARCH64_USER_CACHE_ENABLE))
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