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CI: simulation and HW build with LLVM on RISCV #110

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merged 1 commit into from
Jan 11, 2024
Merged

CI: simulation and HW build with LLVM on RISCV #110

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6 changes: 2 additions & 4 deletions .github/workflows/sel4test-hw.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -33,11 +33,9 @@ jobs:
strategy:
fail-fast: false
matrix:
march: [armv7a, armv8a, nehalem]
# There is no "rv32imac" hardware yet.
march: [armv7a, armv8a, nehalem, rv64imac]
compiler: [gcc, clang]
include:
- march: rv64imac
compiler: gcc
steps:
- name: Build
uses: seL4/ci-actions/sel4test-hw@master
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5 changes: 0 additions & 5 deletions .github/workflows/sel4test-sim.yml
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Expand Up @@ -21,11 +21,6 @@ jobs:
matrix:
march: [armv7a, armv8a, nehalem, rv32imac, rv64imac]
compiler: [gcc, clang]
exclude:
- march: rv32imac
compiler: clang
- march: rv64imac
compiler: clang
steps:
- uses: seL4/ci-actions/sel4test-sim@master
with:
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