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Remove usage of unstable proc macro features #63

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merged 4 commits into from
Jan 11, 2024
Merged

Remove usage of unstable proc macro features #63

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22b08e4
Help rustfmt with dummy module declarations
nspin Jan 10, 2024
737d144
Add to unstable feature wishlist
nspin Jan 10, 2024
c8afdcd
crates/sel4/config: Add sel4_cfg_wrap_match! macro
nspin Jan 9, 2024
ef342b8
Remove unstable macro-related features
nspin Jan 9, 2024
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78 changes: 41 additions & 37 deletions crates/sel4-capdl-initializer/core/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@

#![no_std]
#![feature(never_type)]
#![feature(proc_macro_hygiene)]
#![feature(stmt_expr_attributes)]

use core::array;
use core::borrow::BorrowMut;
Expand Down Expand Up @@ -103,8 +101,11 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
self.init_frames()?;
self.init_vspaces()?;

#[sel4::sel4_cfg(KERNEL_MCS)]
self.init_sched_contexts()?;
sel4::sel4_cfg_if! {
if #[cfg(KERNEL_MCS)] {
self.init_sched_contexts()?;
}
}

self.init_tcbs()?;
self.init_cspaces()?;
Expand Down Expand Up @@ -329,33 +330,34 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
{
for IRQEntry { irq, handler } in self.spec().irqs.iter() {
let slot = self.cslot_alloc_or_panic();
#[sel4::sel4_cfg_match]
match self.spec().object(*handler) {
Object::IRQ(_) => {
BootInfo::irq_control()
.irq_control_get(*irq, &cslot_relative_cptr(slot))?;
}
#[sel4_cfg(any(ARCH_AARCH32, ARCH_AARCH64))]
Object::ArmIRQ(obj) => {
sel4::sel4_cfg_if! {
if #[cfg(MAX_NUM_NODES = "1")] {
BootInfo::irq_control().irq_control_get_trigger(
*irq,
obj.extra.trigger,
&cslot_relative_cptr(slot),
)?;
} else {
BootInfo::irq_control().irq_control_get_trigger_core(
*irq,
obj.extra.trigger,
obj.extra.target,
&cslot_relative_cptr(slot),
)?;
sel4::sel4_cfg_wrap_match! {
match self.spec().object(*handler) {
Object::IRQ(_) => {
BootInfo::irq_control()
.irq_control_get(*irq, &cslot_relative_cptr(slot))?;
}
#[sel4_cfg(any(ARCH_AARCH32, ARCH_AARCH64))]
Object::ArmIRQ(obj) => {
sel4::sel4_cfg_if! {
if #[cfg(MAX_NUM_NODES = "1")] {
BootInfo::irq_control().irq_control_get_trigger(
*irq,
obj.extra.trigger,
&cslot_relative_cptr(slot),
)?;
} else {
BootInfo::irq_control().irq_control_get_trigger_core(
*irq,
obj.extra.trigger,
obj.extra.target,
&cslot_relative_cptr(slot),
)?;
}
}
}
}
_ => {
panic!();
_ => {
panic!();
}
}
}
self.set_orig_cslot(*handler, slot);
Expand Down Expand Up @@ -578,11 +580,12 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
tcb.tcb_bind_notification(bound_notification)?;
}

#[sel4::sel4_cfg(all(ARCH_AARCH64, ARM_HYPERVISOR_SUPPORT))]
{
if let Some(vcpu) = obj.vcpu() {
let vcpu = self.orig_local_cptr::<cap_type::VCPU>(vcpu.object);
vcpu.vcpu_set_tcb(tcb)?;
sel4::sel4_cfg_if! {
if #[cfg(all(ARCH_AARCH64, ARM_HYPERVISOR_SUPPORT))] {
if let Some(vcpu) = obj.vcpu() {
let vcpu = self.orig_local_cptr::<cap_type::VCPU>(vcpu.object);
vcpu.vcpu_set_tcb(tcb)?;
}
}
}

Expand Down Expand Up @@ -675,9 +678,10 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
prio,
)?;

#[sel4::sel4_cfg(not(MAX_NUM_NODES = "1"))]
{
tcb.tcb_set_affinity(affinity.try_into().unwrap())?;
sel4::sel4_cfg_if! {
if #[cfg(not(MAX_NUM_NODES = "1"))] {
tcb.tcb_set_affinity(affinity.try_into().unwrap())?;
}
}
}
}
Expand Down
2 changes: 0 additions & 2 deletions crates/sel4-capdl-initializer/types/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@

#![cfg_attr(not(feature = "std"), no_std)]
#![feature(never_type)]
#![feature(proc_macro_hygiene)]
#![feature(stmt_expr_attributes)]
#![feature(unwrap_infallible)]

#[cfg(feature = "alloc")]
Expand Down
3 changes: 1 addition & 2 deletions crates/sel4-capdl-initializer/types/src/when_sel4.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,7 @@ use crate::{cap, Badge, Cap, FillEntryContentBootInfoId, Object, Rights};

impl<'a, D, M> Object<'a, D, M> {
pub fn blueprint(&self) -> Option<ObjectBlueprint> {
Some({
#[sel4::sel4_cfg_match]
Some(sel4::sel4_cfg_wrap_match! {
match self {
Object::Untyped(obj) => ObjectBlueprint::Untyped {
size_bits: obj.size_bits,
Expand Down
22 changes: 15 additions & 7 deletions crates/sel4-kernel-loader/src/arch/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,16 +4,24 @@
// SPDX-License-Identifier: BSD-2-Clause
//

use sel4_config::sel4_cfg;
use sel4_config::sel4_cfg_if;
use sel4_kernel_loader_payload_types::PayloadInfo;

#[sel4_cfg(ARCH_AARCH64)]
#[path = "aarch64/mod.rs"]
mod imp;
sel4_cfg_if! {
if #[cfg(ARCH_AARCH64)] {
#[path = "aarch64/mod.rs"]
mod imp;
} else if #[cfg(any(ARCH_RISCV64, ARCH_RISCV32))] {
#[path = "riscv/mod.rs"]
mod imp;
}
}

#[sel4_cfg(any(ARCH_RISCV64, ARCH_RISCV32))]
#[path = "riscv/mod.rs"]
mod imp;
// HACK for rustfmt
#[cfg(any())]
mod aarch64;
#[cfg(any())]
mod riscv;

pub(crate) use imp::*;

Expand Down
1 change: 0 additions & 1 deletion crates/sel4-kernel-loader/src/main.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@

#![no_std]
#![no_main]
#![feature(proc_macro_hygiene)]
#![allow(dead_code)]
#![allow(unreachable_code)]
#![allow(clippy::reversed_empty_ranges)]
Expand Down
33 changes: 21 additions & 12 deletions crates/sel4-kernel-loader/src/plat/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,19 +4,28 @@
// SPDX-License-Identifier: BSD-2-Clause
//

use sel4_config::sel4_cfg;

#[sel4_cfg(all(ARCH_AARCH64, PLAT_QEMU_ARM_VIRT))]
#[path = "qemu_arm_virt/mod.rs"]
mod imp;

#[sel4_cfg(all(ARCH_AARCH64, PLAT_BCM2711))]
#[path = "bcm2711/mod.rs"]
mod imp;
use sel4_config::sel4_cfg_if;

sel4_cfg_if! {
if #[cfg(all(ARCH_AARCH64, PLAT_QEMU_ARM_VIRT))] {
#[path = "qemu_arm_virt/mod.rs"]
mod imp;
} else if #[cfg(all(ARCH_AARCH64, PLAT_BCM2711))] {
#[path = "bcm2711/mod.rs"]
mod imp;
} else if #[cfg(all(any(ARCH_RISCV64, ARCH_RISCV32), any(PLAT_SPIKE, PLAT_QEMU_RISCV_VIRT)))] {
#[path = "riscv_generic/mod.rs"]
mod imp;
}
}

#[sel4_cfg(all(any(ARCH_RISCV64, ARCH_RISCV32), any(PLAT_SPIKE, PLAT_QEMU_RISCV_VIRT)))]
#[path = "riscv_generic/mod.rs"]
mod imp;
// HACK for rustfmt
#[cfg(any())]
mod bcm2711;
#[cfg(any())]
mod qemu_arm_virt;
#[cfg(any())]
mod riscv_generic;

#[allow(unused_imports)]
pub(crate) use imp::*;
Expand Down
8 changes: 8 additions & 0 deletions crates/sel4/config/generic/macro-impls/src/attr_macros.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,14 @@ impl<'a> Impls<'a> {

pub fn cfg_match_impl(&self, input: TokenStream, item: TokenStream) -> TokenStream {
ensure_empty!(input);
self.cfg_match_impl_inner(item)
}

pub fn cfg_wrap_match_impl(&self, item: TokenStream) -> TokenStream {
self.cfg_match_impl_inner(item)
}

fn cfg_match_impl_inner(&self, item: TokenStream) -> TokenStream {
let mut match_expr = parse_or_return!(item as syn::ExprMatch);
let mut helper = Helper::new(self);
match_expr
Expand Down
5 changes: 5 additions & 0 deletions crates/sel4/config/macros/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,11 @@ pub fn sel4_cfg_match(input: TokenStream, item: TokenStream) -> TokenStream {
get_impls().cfg_match_impl(input.into(), item.into()).into()
}

#[proc_macro]
pub fn sel4_cfg_wrap_match(item: TokenStream) -> TokenStream {
get_impls().cfg_wrap_match_impl(item.into()).into()
}

#[proc_macro]
pub fn sel4_cfg_if(toks: TokenStream) -> TokenStream {
get_impls().cfg_if_impl(toks.into()).into()
Expand Down
9 changes: 8 additions & 1 deletion crates/sel4/src/arch/arm/arch/aarch32/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,14 @@ mod fault;
mod object;
mod user_context;

#[sel4_config::sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sel4_config::sel4_cfg_if! {
if #[cfg(ARM_HYPERVISOR_SUPPORT)] {
mod vcpu_reg;
}
}

// HACK for rustfmt
#[cfg(any())]
mod vcpu_reg;

pub(crate) mod top_level {
Expand Down
9 changes: 8 additions & 1 deletion crates/sel4/src/arch/arm/arch/aarch64/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,14 @@ mod fault;
mod object;
mod user_context;

#[sel4_config::sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sel4_config::sel4_cfg_if! {
if #[cfg(ARM_HYPERVISOR_SUPPORT)] {
mod vcpu_reg;
}
}

// HACK for rustfmt
#[cfg(any())]
mod vcpu_reg;

pub(crate) mod top_level {
Expand Down
22 changes: 15 additions & 7 deletions crates/sel4/src/arch/arm/arch/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,22 @@
// SPDX-License-Identifier: MIT
//

use sel4_config::sel4_cfg;
use sel4_config::sel4_cfg_if;

#[sel4_cfg(ARCH_AARCH64)]
#[path = "aarch64/mod.rs"]
mod imp;
sel4_cfg_if! {
if #[cfg(ARCH_AARCH64)] {
#[path = "aarch64/mod.rs"]
mod imp;
} else if #[cfg(ARCH_AARCH32)] {
#[path = "aarch32/mod.rs"]
mod imp;
}
}

#[sel4_cfg(ARCH_AARCH32)]
#[path = "aarch32/mod.rs"]
mod imp;
// HACK for rustfmt
#[cfg(any())]
mod aarch32;
#[cfg(any())]
mod aarch64;

pub(crate) use imp::*;
55 changes: 28 additions & 27 deletions crates/sel4/src/arch/arm/fault.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
// SPDX-License-Identifier: MIT
//

use sel4_config::{sel4_cfg, sel4_cfg_enum, sel4_cfg_if, sel4_cfg_match};
use sel4_config::{sel4_cfg, sel4_cfg_enum, sel4_cfg_if, sel4_cfg_wrap_match};

use crate::{declare_fault_newtype, sys, Word};

Expand Down Expand Up @@ -46,32 +46,33 @@ pub enum Fault {

impl Fault {
pub fn from_sys(raw: sys::seL4_Fault) -> Self {
#[sel4_cfg_match]
match raw.splay() {
sys::seL4_Fault_Splayed::NullFault(inner) => {
Self::NullFault(NullFault::from_inner(inner))
}
sys::seL4_Fault_Splayed::CapFault(inner) => Self::CapFault(CapFault::from_inner(inner)),
sys::seL4_Fault_Splayed::UnknownSyscall(inner) => {
Self::UnknownSyscall(UnknownSyscall::from_inner(inner))
}
sys::seL4_Fault_Splayed::UserException(inner) => {
Self::UserException(UserException::from_inner(inner))
}
sys::seL4_Fault_Splayed::VMFault(inner) => Self::VMFault(VMFault::from_inner(inner)),
#[sel4_cfg(KERNEL_MCS)]
sys::seL4_Fault_Splayed::Timeout(inner) => Self::Timeout(Timeout::from_inner(inner)),
#[sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sys::seL4_Fault_Splayed::VGICMaintenance(inner) => {
Self::VGICMaintenance(VGICMaintenance::from_inner(inner))
}
#[sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sys::seL4_Fault_Splayed::VCPUFault(inner) => {
Self::VCPUFault(VCPUFault::from_inner(inner))
}
#[sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sys::seL4_Fault_Splayed::VPPIEvent(inner) => {
Self::VPPIEvent(VPPIEvent::from_inner(inner))
sel4_cfg_wrap_match! {
match raw.splay() {
sys::seL4_Fault_Splayed::NullFault(inner) => {
Self::NullFault(NullFault::from_inner(inner))
}
sys::seL4_Fault_Splayed::CapFault(inner) => Self::CapFault(CapFault::from_inner(inner)),
sys::seL4_Fault_Splayed::UnknownSyscall(inner) => {
Self::UnknownSyscall(UnknownSyscall::from_inner(inner))
}
sys::seL4_Fault_Splayed::UserException(inner) => {
Self::UserException(UserException::from_inner(inner))
}
sys::seL4_Fault_Splayed::VMFault(inner) => Self::VMFault(VMFault::from_inner(inner)),
#[sel4_cfg(KERNEL_MCS)]
sys::seL4_Fault_Splayed::Timeout(inner) => Self::Timeout(Timeout::from_inner(inner)),
#[sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sys::seL4_Fault_Splayed::VGICMaintenance(inner) => {
Self::VGICMaintenance(VGICMaintenance::from_inner(inner))
}
#[sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sys::seL4_Fault_Splayed::VCPUFault(inner) => {
Self::VCPUFault(VCPUFault::from_inner(inner))
}
#[sel4_cfg(ARM_HYPERVISOR_SUPPORT)]
sys::seL4_Fault_Splayed::VPPIEvent(inner) => {
Self::VPPIEvent(VPPIEvent::from_inner(inner))
}
}
}
}
Expand Down
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