Extend support for riscv32 beyond sel4-sys

seL4 · Sep 12, 2023 · 4fa7fb5 · 4fa7fb5
1 parent 3fe879a
commit 4fa7fb5
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Showing 80 changed files with 1,081 additions and 614 deletions.
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/crates/examples/root-task/example-root-task-without-runtime/src/main.rs b/crates/examples/root-task/example-root-task-without-runtime/src/main.rs
@@ -116,30 +116,52 @@ cfg_if::cfg_if! {
                 1:  b 1b
             "#
         }
-    } else if #[cfg(target_arch = "riscv64")] {
+    } else if #[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))] {
+        macro_rules! riscv_common {
+            () => {
+                r#"
+                    .extern __rust_entry
+                    .extern __stack_top
+
+                    .section .text
+
+                    .global _start
+                    _start:
+
+                        # See https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain
+                    .option push
+                    .option norelax
+                    1:  auipc gp, %pcrel_hi(__global_pointer$)
+                        addi gp, gp, %pcrel_lo(1b)
+                    .option pop
+
+                        la sp, __stack_top
+                        lx sp, (sp)
+                        jal __rust_entry
+
+                    1:  j 1b
+                "#
+            }
+        }
+
+        #[cfg(target_arch = "riscv64")]
         global_asm! {
             r#"
-                .extern __rust_entry
-                .extern __sel4_runtime_stack_top
-
-                .section .text
-
-                .global _start
-                _start:
-
-                    # See https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain
-                .option push
-                .option norelax
-                1:  auipc gp, %pcrel_hi(__global_pointer$)
-                    addi gp, gp, %pcrel_lo(1b)
-                .option pop
-
-                    la sp, __stack_top
-                    ld sp, (sp)
-                    jal __rust_entry
+                .macro lx dst, src
+                    ld \dst, \src
+                .endm
+            "#,
+            riscv_common!()
+        }
 
-                1:  j 1b
-            "#
+        #[cfg(target_arch = "riscv32")]
+        global_asm! {
+            r#"
+                .macro lx dst, src
+                    lw \dst, \src
+                .endm
+            "#,
+            riscv_common!()
         }
     } else if #[cfg(target_arch = "x86_64")] {
         global_asm! {

diff --git a/crates/private/support/sel4-simple-task/threading/src/lib.rs b/crates/private/support/sel4-simple-task/threading/src/lib.rs
@@ -2,12 +2,12 @@
 
 use core::mem;
 
-use sel4::{Endpoint, RecvWithMRs, ReplyAuthority};
+use sel4::{Endpoint, RecvWithMRs, ReplyAuthority, Word};
 
 #[cfg(feature = "alloc")]
 extern crate alloc;
 
-pub type StaticThreadEntryFn = extern "C" fn(arg0: u64, arg1: u64);
+pub type StaticThreadEntryFn = extern "C" fn(arg0: Word, arg1: Word);
 
 #[derive(Copy, Clone, Debug)]
 pub struct StaticThread(Endpoint);
@@ -54,7 +54,7 @@ mod when_alloc {
         }
     }
 
-    extern "C" fn entry(f_arg: u64) {
+    extern "C" fn entry(f_arg: Word) {
         let f = unsafe { Box::from_raw(f_arg as *mut Box<dyn FnOnce()>) };
         let _ = catch_unwind(f);
     }

diff --git a/crates/sel4-backtrace/addr2line-context-helper/Cargo.toml b/crates/sel4-backtrace/addr2line-context-helper/Cargo.toml
@@ -6,10 +6,10 @@ edition = "2021"
 license = "BSD-2-Clause"
 
 [dependencies]
-gimli = { version = "0.27.2", default-features = false, features = ["endian-reader"] }
+gimli = { version = "0.28.0", default-features = false, features = ["endian-reader"] }
 stable_deref_trait = { version = "1.1.0", default-features = false, features = ["alloc"] }
 
 [dependencies.addr2line]
-version = "0.20.0"
+version = "0.21.0"
 default-features = false
 features = ["rustc-demangle", "cpp_demangle", "fallible-iterator", "smallvec", "object"]