fix typo for RISC-V 32-bit

Signed-off-by: Axel Heider <[email protected]>
seL4 · Jan 9, 2024 · ea09f16 · ea09f16
1 parent 702d24c
commit ea09f16
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/seL4-platforms/platforms.py b/seL4-platforms/platforms.py
@@ -187,7 +187,7 @@ def getISA(self, mode: int) -> str:
             return {32: "IA32", 64: "x86_64"}[mode]
 
         if self.arch == "riscv":
-            return {32: "RC32IMAC", 64: "RV64IMAC"}[mode]
+            return {32: "RV32IMAC", 64: "RV64IMAC"}[mode]
 
         return self.march.capitalize()