include all opcodes in rv32im config

scroll-tech · Oct 29, 2024 · 9dd45db · 9dd45db
1 parent b24c98a
commit 9dd45db
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Showing 11 changed files with 245 additions and 91 deletions.
diff --git a/ceno_zkvm/examples/fibonacci_elf.rs b/ceno_zkvm/examples/fibonacci_elf.rs
@@ -11,6 +11,7 @@ use ceno_zkvm::{
     structs::{ZKVMConstraintSystem, ZKVMFixedTraces, ZKVMWitnesses},
     tables::{MemFinalRecord, ProgramTableCircuit, initial_memory, initial_registers},
 };
+use ff_ext::ff::Field;
 use goldilocks::GoldilocksExt2;
 use itertools::Itertools;
 use mpcs::{Basefold, BasefoldRSParams, PolynomialCommitmentScheme};
@@ -19,7 +20,6 @@ use std::{panic, time::Instant};
 use tracing_flame::FlameLayer;
 use tracing_subscriber::{EnvFilter, Registry, fmt, layer::SubscriberExt};
 use transcript::Transcript;
-use ff_ext::ff::Field;
 
 fn main() {
     type E = GoldilocksExt2;
@@ -153,7 +153,7 @@ fn main() {
         .assign_table_circuit::<ExampleProgramTableCircuit<E>>(
             &zkvm_cs,
             &prog_config,
-            &vm.program(),
+            vm.program(),
         )
         .unwrap();
 

diff --git a/ceno_zkvm/src/instructions/riscv/branch.rs b/ceno_zkvm/src/instructions/riscv/branch.rs
@@ -25,22 +25,22 @@ pub struct BltuOp;
 impl RIVInstruction for BltuOp {
     const INST_KIND: InsnKind = InsnKind::BLTU;
 }
-pub type BltuInstruction = bltu::BltuCircuit<BltuOp>;
+pub type BltuInstruction<E> = bltu::BltuCircuit<E, BltuOp>;
 
 pub struct BgeuOp;
 impl RIVInstruction for BgeuOp {
     const INST_KIND: InsnKind = InsnKind::BGEU;
 }
-pub type BgeuInstruction = bltu::BltuCircuit<BgeuOp>;
+pub type BgeuInstruction<E> = bltu::BltuCircuit<E, BgeuOp>;
 
 pub struct BltOp;
 impl RIVInstruction for BltOp {
     const INST_KIND: InsnKind = InsnKind::BLT;
 }
-pub type BltInstruction = blt::BltCircuit<BltOp>;
+pub type BltInstruction<E> = blt::BltCircuit<E, BltOp>;
 
 pub struct BgeOp;
 impl RIVInstruction for BgeOp {
     const INST_KIND: InsnKind = InsnKind::BGE;
 }
-pub type BgeInstruction = blt::BltCircuit<BgeOp>;
+pub type BgeInstruction<E> = blt::BltCircuit<E, BgeOp>;
diff --git a/ceno_zkvm/src/instructions/riscv/branch/blt.rs b/ceno_zkvm/src/instructions/riscv/branch/blt.rs
@@ -16,7 +16,7 @@ use crate::{
 };
 use ceno_emul::{InsnKind, SWord};
 
-pub struct BltCircuit<I>(PhantomData<I>);
+pub struct BltCircuit<E, I>(PhantomData<(E, I)>);
 
 pub struct InstructionConfig<E: ExtensionField> {
     pub b_insn: BInstructionConfig<E>,
@@ -25,7 +25,7 @@ pub struct InstructionConfig<E: ExtensionField> {
     pub signed_lt: SignedLtConfig,
 }
 
-impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for BltCircuit<I> {
+impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for BltCircuit<E, I> {
     fn name() -> String {
         format!("{:?}", I::INST_KIND)
     }

diff --git a/ceno_zkvm/src/instructions/riscv/branch/bltu.rs b/ceno_zkvm/src/instructions/riscv/branch/bltu.rs
@@ -20,7 +20,7 @@ use crate::{
 };
 use ceno_emul::InsnKind;
 
-pub struct BltuCircuit<I>(PhantomData<I>);
+pub struct BltuCircuit<E, I>(PhantomData<(E, I)>);
 
 pub struct InstructionConfig<E: ExtensionField> {
     pub b_insn: BInstructionConfig<E>,
@@ -29,7 +29,7 @@ pub struct InstructionConfig<E: ExtensionField> {
     pub is_lt: IsLtConfig,
 }
 
-impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for BltuCircuit<I> {
+impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for BltuCircuit<E, I> {
     fn name() -> String {
         format!("{:?}", I::INST_KIND)
     }

diff --git a/ceno_zkvm/src/instructions/riscv/jump/jalr.rs b/ceno_zkvm/src/instructions/riscv/jump/jalr.rs
@@ -109,6 +109,10 @@ impl<E: ExtensionField> Instruction<E> for JalrInstruction<E> {
 
         let rs1 = step.rs1().unwrap().value;
         let imm: i32 = insn.imm_or_funct7() as i32;
+        if step.rd().is_none() {
+            tracing::info!("step: {:?}", step.insn().kind());
+            tracing::info!("step: {:?}", step);
+        }
         let rd = step.rd().unwrap().value.after;
 
         let (sum, overflowing) = rs1.overflowing_add_signed(imm);

diff --git a/ceno_zkvm/src/instructions/riscv/memory/store.rs b/ceno_zkvm/src/instructions/riscv/memory/store.rs
@@ -38,7 +38,6 @@ impl RIVInstruction for SWOp {
     const INST_KIND: InsnKind = InsnKind::SW;
 }
 
-#[cfg(test)]
 pub type SwInstruction<E> = StoreInstruction<E, SWOp, 2>;
 
 pub struct SHOp;
@@ -47,7 +46,6 @@ impl RIVInstruction for SHOp {
     const INST_KIND: InsnKind = InsnKind::SH;
 }
 
-#[cfg(test)]
 pub type ShInstruction<E> = StoreInstruction<E, SHOp, 1>;
 
 pub struct SBOp;
@@ -56,7 +54,6 @@ impl RIVInstruction for SBOp {
     const INST_KIND: InsnKind = InsnKind::SB;
 }
 
-#[cfg(test)]
 pub type SbInstruction<E> = StoreInstruction<E, SBOp, 0>;
 
 impl<E: ExtensionField, I: RIVInstruction, const N_ZEROS: usize> Instruction<E>