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riscv: Apply Zawrs when available #172

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merged 4 commits into from
Sep 3, 2024
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@cp0613 cp0613 commented Sep 2, 2024

These patches come from the upstream community to support zawrs extension.
The latest XuanTie C920 processor supports this extension.

Link: https://lore.kernel.org/all/[email protected]/

@cp0613 cp0613 force-pushed the linux-6.6.36 branch 2 times, most recently from b7dcd46 to 69f20bf Compare September 3, 2024 01:31
jones-drew and others added 4 commits September 3, 2024 09:36
If we're going to provide the encoding for 'pause' in cpu_relax()
anyway, then we can drop the toolchain checks and just always use
it. The advantage of doing this is that other code that need
pause don't need to also define it (yes, another use is coming).
Add the definition to insn-def.h since it's an instruction
definition and also because insn-def.h doesn't include much, so
it's safe to include from asm/vdso/processor.h without concern for
circular dependencies.

Signed-off-by: Andrew Jones <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Chen Pei <[email protected]>
Add description for the Zawrs (Wait-on-Reservation-Set) ISA extension
which was ratified of riscv-isa-manual.

Signed-off-by: Andrew Jones <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Chen Pei <[email protected]>
RISC-V code uses the generic ticket lock implementation, which calls
the macros smp_cond_load_relaxed() and smp_cond_load_acquire().
Introduce a RISC-V specific implementation of smp_cond_load_relaxed()
which applies WRS.NTO of the Zawrs extension in order to reduce power
consumption while waiting and allows hypervisors to enable guests to
trap while waiting. smp_cond_load_acquire() doesn't need a RISC-V
specific implementation as the generic implementation is based on
smp_cond_load_relaxed() and smp_acquire__after_ctrl_dep() sufficiently
provides the acquire semantics.

This implementation is heavily based on Arm's approach which is the
approach Andrea Parri also suggested.

The Zawrs specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc

Signed-off-by: Christoph Müllner <[email protected]>
Co-developed-by: Andrew Jones <[email protected]>
Signed-off-by: Andrew Jones <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Chen Pei <[email protected]>
Kconfig: If the toolchain or cpu does not support the zawrs extension
we should not enable it.

th1520_defconfig: Enable CONFIG_JUMP_LABEL to optimize performance
and resolve compilation errors.

Signed-off-by: Chen Pei <[email protected]>
@RevySR RevySR merged commit 7c000ca into ruyisdk:linux-6.6.36 Sep 3, 2024
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4 participants