T-Head C9xx cores implement an older version (0.7.1) of the vector

specification. Relevant changes concerning the kernel are: - different placement of the SR_VS bit for the vector unit status - different encoding of the vsetvli instruction - different instructions for loads and stores And a fixed VLEN of 128. The in-kernel access to vector instances is limited to the save and restore of process states so the above mentioned areas can simply be handled via the alternatives framework, similar to other T-Head specific issues. TODO: FIXME: Do real vstate discard in __riscv_v_vstate_discard! Co-developed-by: Heiko Stuebner <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Co-developed-by: Guo Ren <[email protected]> Signed-off-by: Guo Ren <[email protected]> Co-developed-by: Chen Pei <[email protected]> Signed-off-by: Chen Pei <[email protected]> Co-developed-by: Han Gao <[email protected]> Signed-off-by: Han Gao <[email protected]>
ruyisdk · Jun 29, 2024 · 9fb5fcf · 9fb5fcf
1 parent ed3b5e7
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Showing 6 changed files with 221 additions and 24 deletions.
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
@@ -99,4 +99,17 @@ config ERRATA_THEAD_PMU
 
 	  If you don't know what to do here, say "Y".
 
+config ERRATA_THEAD_VECTOR
+	bool "Apply T-Head Vector errata"
+	depends on ERRATA_THEAD && RISCV_ISA_V && !ARCH_RV32I
+	default y
+	help
+	  The T-Head C9xx cores implement an earlier version 0.7.1
+	  of the vector extensions.
+
+	  This will apply the necessary errata to handle the non-standard
+	  behaviour via when switch to and from vector mode for processes.
+
+	  If you don't know what to do here, say "Y".
+
 endmenu # "CPU errata selection"
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
@@ -15,6 +15,7 @@
 #include <asm/errata_list.h>
 #include <asm/hwprobe.h>
 #include <asm/patch.h>
+#include <asm/vector.h>
 #include <asm/vendorid_list.h>
 
 static bool errata_probe_pbmt(unsigned int stage,
@@ -33,6 +34,22 @@ static bool errata_probe_pbmt(unsigned int stage,
 	return false;
 }
 
+static bool errata_probe_vector(unsigned int stage,
+		unsigned long arch_id, unsigned long impid)
+{
+	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_VECTOR))
+		return false;
+
+	/* target-c9xx cores report arch_id and impid as 0 */
+	if (arch_id != 0 || impid != 0)
+		return false;
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return false;
+
+	return true;
+}
+
 static bool errata_probe_cmo(unsigned int stage,
 			     unsigned long arch_id, unsigned long impid)
 {
@@ -83,6 +100,9 @@ static u32 thead_errata_probe(unsigned int stage,
 	if (errata_probe_pmu(stage, archid, impid))
 		cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
 
+	if (errata_probe_vector(stage, archid, impid))
+		cpu_req_errata |= BIT(ERRATA_THEAD_VECTOR);
+
 	return cpu_req_errata;
 }
 

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
@@ -38,6 +38,16 @@
 #define SR_VS_CLEAN	_AC(0x00000400, UXL)
 #define SR_VS_DIRTY	_AC(0x00000600, UXL)
 
+#define SR_VS_THEAD	_AC(0x01800000, UXL) /* Vector Status */
+#define SR_VS_OFF_THEAD	_AC(0x00000000, UXL)
+#define SR_VS_INITIAL_THEAD _AC(0x00800000, UXL)
+#define SR_VS_CLEAN_THEAD _AC(0x01000000, UXL)
+#define SR_VS_DIRTY_THEAD _AC(0x01800000, UXL)
+/* VCSR flags */
+#define VCSR_VXRM_MASK			3
+#define VCSR_VXRM_SHIFT			1
+#define VCSR_VXSAT_MASK			1
+
 #define SR_MS		_AC(0x06000000, UXL) /* Matrix Status */
 #define SR_MS_OFF	_AC(0x00000000, UXL)
 #define SR_MS_INITIAL	_AC(0x02000000, UXL)
@@ -50,7 +60,7 @@
 #define SR_XS_CLEAN	_AC(0x00010000, UXL)
 #define SR_XS_DIRTY	_AC(0x00018000, UXL)
 
-#define SR_FS_VS	(SR_FS | SR_VS | SR_MS) /* Vector and Floating-Point Unit */
+#define SR_FS_VS	(SR_FS | SR_VS | SR_MS | SR_VS_THEAD) /* Vector and Floating-Point Unit */
 
 #if __riscv_xlen == 32
 #define SR_SD		_AC(0x80000000, UXL) /* FS/VS/XS dirty */

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
@@ -26,7 +26,8 @@
 #define	ERRATA_THEAD_PBMT 0
 #define	ERRATA_THEAD_CMO 1
 #define	ERRATA_THEAD_PMU 2
-#define	ERRATA_THEAD_NUMBER 3
+#define ERRATA_THEAD_VECTOR 3
+#define	ERRATA_THEAD_NUMBER 4
 #endif
 
 #ifdef __ASSEMBLY__
@@ -164,6 +165,49 @@ asm volatile(ALTERNATIVE(						\
 	: "=r" (__ovl) :						\
 	: "memory")
 
+#define THEAD_C9XX_CSR_VXSAT			0x9
+#define THEAD_C9XX_CSR_VXRM			0xa
+
+	/*
+	 * Vector 0.7.1 as used for example on T-Head Xuantie cores, uses an older
+	 * encoding for vsetvli (ta, ma vs. d1), so provide an instruction for
+	 * vsetvli	t4, x0, e8, m8, d1
+	 */
+#define THEAD_VSETVLI_T4X0E8M8D1	".long	0x00307ed7\n\t"
+
+	/*
+	 * While in theory, the vector-0.7.1 vsb.v and vlb.v result in the same
+	 * encoding as the standard vse8.v and vle8.v, compilers seem to optimize
+	 * the call resulting in a different encoding and then using a value for
+	 * the "mop" field that is not part of vector-0.7.1
+	 * So encode specific variants for vstate_save and _restore.
+	 */
+#define THEAD_VSB_V_V0T0		".long	0x02028027\n\t"
+#define THEAD_VSB_V_V8T0		".long	0x02028427\n\t"
+#define THEAD_VSB_V_V16T0		".long	0x02028827\n\t"
+#define THEAD_VSB_V_V24T0		".long	0x02028c27\n\t"
+#define THEAD_VLB_V_V0T0		".long	0x012028007\n\t"
+#define THEAD_VLB_V_V8T0		".long	0x012028407\n\t"
+#define THEAD_VLB_V_V16T0		".long	0x012028807\n\t"
+#define THEAD_VLB_V_V24T0		".long	0x012028c07\n\t"
+
+#define ALT_SR_VS_VECTOR_1_0_SHIFT	9
+#define ALT_SR_VS_THEAD_SHIFT		23
+
+#ifdef CONFIG_ERRATA_THEAD_VECTOR
+#define ALT_SR_VS(_val, prot)							\
+	asm(ALTERNATIVE("li %0, %1\t\nslli %0,%0,%3",				\
+			"li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,		\
+			ERRATA_THEAD_VECTOR, CONFIG_ERRATA_THEAD_VECTOR)	\
+			: "=r"(_val)						\
+			: "I"(prot >> ALT_SR_VS_VECTOR_1_0_SHIFT),		\
+			  "I"(prot##_THEAD >> ALT_SR_VS_THEAD_SHIFT),		\
+			  "I"(ALT_SR_VS_VECTOR_1_0_SHIFT),			\
+			  "I"(ALT_SR_VS_THEAD_SHIFT))
+#else
+#define ALT_SR_VS(_val, prot) _val = prot;
+#endif /* CONFIG_ERRATA_THEAD_VECTOR */
+
 #endif /* __ASSEMBLY__ */
 
 #endif