refactor: remove global cycle

WIP.md

@@ -7,6 +7,7 @@
 
 - easy chores:
 
+  - move functional units into package
   - rename crates and github repo
   - publish to crates.io
   - publish python package to pip
@@ -31,6 +32,8 @@
 
     - asynchronously push into file (unordered)
 
+  - DONE: pipelined simd function unit should not implement simd function unit
+  - DONE: get rid of global cycle mutex
   - DONE: lint
   - DONE: execution driven frontend
   - DONE: refactor events

src/cache/base.rs

@@ -2,7 +2,7 @@ use crate::{
     address, config, interconn as ic, mem_fetch,
     mem_sub_partition::SECTOR_SIZE,
     mshr::{self, MSHR},
-    tag_array, Cycle,
+    tag_array,
 };
 use console::style;
 use std::collections::{HashMap, VecDeque};
@@ -32,7 +32,6 @@ pub struct Base<I> {
     pub name: String,
     pub core_id: usize,
     pub cluster_id: usize,
-    pub cycle: Cycle,
 
     pub stats: Arc<Mutex<stats::Cache>>,
     pub config: Arc<config::GPU>,
@@ -65,7 +64,6 @@ impl<I> Base<I> {
         name: String,
         core_id: usize,
         cluster_id: usize,
-        cycle: Cycle,
         mem_port: Arc<I>,
         stats: Arc<Mutex<stats::Cache>>,
         config: Arc<config::GPU>,
@@ -84,7 +82,6 @@ impl<I> Base<I> {
             name,
             core_id,
             cluster_id,
-            cycle,
             tag_array,
             mshrs,
             mem_port,
@@ -264,12 +261,12 @@ impl<I> Base<I> {
     }
 }
 
-impl<I> super::Component for Base<I>
+impl<I> crate::engine::cycle::Component for Base<I>
 where
     I: ic::MemFetchInterface,
 {
     /// Sends next request to lower level of memory
-    fn cycle(&mut self) {
+    fn cycle(&mut self, cycle: u64) {
         use super::Bandwidth;
         log::debug!(
             "{}::baseline cache::cycle (fetch interface {:?}) miss queue={:?}",
@@ -293,8 +290,7 @@ where
                         fetch.data_size(),
                         fetch.control_size(),
                     );
-                    let time = self.cycle.get();
-                    self.mem_port.push(fetch, time);
+                    self.mem_port.push(fetch, cycle);
                 }
             }
         }

src/cache/data.rs

@@ -1,4 +1,4 @@
-use crate::{address, cache, config, interconn as ic, mem_fetch, mshr::MSHR, tag_array, Cycle};
+use crate::{address, cache, config, interconn as ic, mem_fetch, mshr::MSHR, tag_array};
 use std::collections::VecDeque;
 use std::sync::{Arc, Mutex};
 
@@ -24,7 +24,6 @@ where
         name: String,
         core_id: usize,
         cluster_id: usize,
-        cycle: Cycle,
         mem_port: Arc<I>,
         stats: Arc<Mutex<stats::Cache>>,
         config: Arc<config::GPU>,
@@ -36,7 +35,6 @@ where
             name,
             core_id,
             cluster_id,
-            cycle,
             mem_port,
             stats,
             config,
@@ -510,7 +508,6 @@ where
         //
         // Function pointers were used to avoid many long conditional
         // branches resulting from many cache configuration options.
-        // let time = self.inner.cycle.get();
         let mut access_status = probe_status;
         let data_size = fetch.data_size();
 
@@ -561,12 +558,12 @@ where
     }
 }
 
-impl<I> cache::Component for Data<I>
+impl<I> crate::engine::cycle::Component for Data<I>
 where
     I: ic::MemFetchInterface,
 {
-    fn cycle(&mut self) {
-        self.inner.cycle();
+    fn cycle(&mut self, cycle: u64) {
+        self.inner.cycle(cycle);
     }
 }
 

src/cache/l2.rs

@@ -1,4 +1,4 @@
-use crate::{address, config, interconn as ic, mem_fetch, Cycle};
+use crate::{address, config, interconn as ic, mem_fetch};
 use std::collections::VecDeque;
 use std::sync::{Arc, Mutex};
 
@@ -18,7 +18,6 @@ where
         name: String,
         core_id: usize,
         cluster_id: usize,
-        cycle: Cycle,
         fetch_interconn: Arc<I>,
         stats: Arc<Mutex<stats::Cache>>,
         config: Arc<config::GPU>,
@@ -28,7 +27,6 @@ where
             name,
             core_id,
             cluster_id,
-            cycle,
             fetch_interconn,
             stats,
             config,
@@ -43,12 +41,12 @@ where
     }
 }
 
-impl<I> super::Component for DataL2<I>
+impl<I> crate::engine::cycle::Component for DataL2<I>
 where
     I: ic::MemFetchInterface,
 {
-    fn cycle(&mut self) {
-        self.inner.cycle();
+    fn cycle(&mut self, cycle: u64) {
+        self.inner.cycle(cycle);
     }
 }
 

src/cache/mod.rs

@@ -77,11 +77,7 @@ impl From<AccessStat> for stats::cache::AccessStat {
     }
 }
 
-pub trait Component {
-    fn cycle(&mut self);
-}
-
-pub trait Cache: Send + Sync + Component + Bandwidth + 'static {
+pub trait Cache: crate::engine::cycle::Component + Send + Sync + Bandwidth + 'static {
     fn as_any(&self) -> &dyn std::any::Any;
 
     fn stats(&self) -> &Arc<Mutex<stats::Cache>>;

src/cache/readonly.rs

@@ -1,29 +1,26 @@
-use super::base;
-use crate::{address, cache, config, interconn as ic, mem_fetch, tag_array, Cycle};
+use crate::{address, cache, config, interconn as ic, mem_fetch, tag_array};
 use std::collections::VecDeque;
 use std::sync::{Arc, Mutex};
 
 #[derive(Debug)]
 pub struct ReadOnly<I> {
-    inner: base::Base<I>,
+    inner: cache::base::Base<I>,
 }
 
 impl<I> ReadOnly<I> {
     pub fn new(
         name: String,
         core_id: usize,
         cluster_id: usize,
-        cycle: Cycle,
         mem_port: Arc<I>,
         stats: Arc<Mutex<stats::Cache>>,
         config: Arc<config::GPU>,
         cache_config: Arc<config::Cache>,
     ) -> Self {
-        let inner = base::Base::new(
+        let inner = cache::base::Base::new(
             name,
             core_id,
             cluster_id,
-            cycle,
             mem_port,
             stats,
             config,
@@ -33,12 +30,12 @@ impl<I> ReadOnly<I> {
     }
 }
 
-impl<I> cache::Component for ReadOnly<I>
+impl<I> crate::engine::cycle::Component for ReadOnly<I>
 where
     I: ic::MemFetchInterface,
 {
-    fn cycle(&mut self) {
-        self.inner.cycle();
+    fn cycle(&mut self, cycle: u64) {
+        self.inner.cycle(cycle);
     }
 }
 
@@ -92,9 +89,8 @@ where
     ) -> cache::RequestStatus {
         use cache::RequestStatus as Status;
 
-        let base::Base {
+        let cache::base::Base {
             ref cache_config,
-
             ref mut tag_array,
             ..
         } = self.inner;

src/cluster.rs

@@ -8,7 +8,6 @@ use std::sync::{atomic, Arc, Mutex, RwLock};
 #[derive(Debug)]
 pub struct Cluster<I> {
     pub cluster_id: usize,
-    pub cycle: super::Cycle,
     pub warp_instruction_unique_uid: Arc<atomic::AtomicU64>,
     pub cores: Vec<Arc<RwLock<Core<I>>>>,
     pub config: Arc<config::GPU>,
@@ -27,7 +26,6 @@ where
 {
     pub fn new(
         cluster_id: usize,
-        cycle: &super::Cycle,
         warp_instruction_unique_uid: &Arc<atomic::AtomicU64>,
         allocations: &super::allocation::Ref,
         interconn: &Arc<I>,
@@ -38,7 +36,6 @@ where
         let block_issue_next_core = Mutex::new(num_cores - 1);
         let mut cluster = Self {
             cluster_id,
-            cycle: cycle.clone(),
             warp_instruction_unique_uid: Arc::clone(warp_instruction_unique_uid),
             config: config.clone(),
             stats: stats.clone(),
@@ -56,7 +53,6 @@ where
                     id,
                     cluster_id,
                     Arc::clone(allocations),
-                    cycle.clone(),
                     Arc::clone(warp_instruction_unique_uid),
                     Arc::clone(interconn),
                     Arc::clone(stats),
@@ -91,14 +87,14 @@ where
             .sum()
     }
 
-    pub fn interconn_cycle(&mut self) {
+    pub fn interconn_cycle(&mut self, cycle: u64) {
         use mem_fetch::AccessKind;
 
         log::debug!(
             "{}",
             style(format!(
                 "cycle {:02} cluster {}: interconn cycle (response fifo={:?})",
-                self.cycle.get(),
+                cycle,
                 self.cluster_id,
                 self.response_fifo
                     .iter()
@@ -121,14 +117,14 @@ where
                     } else {
                         let fetch = self.response_fifo.pop_front().unwrap();
                         log::debug!("accepted instr access fetch {}", fetch);
-                        core.accept_fetch_response(fetch);
+                        core.accept_fetch_response(fetch, cycle);
                     }
                 }
                 _ if !core.ldst_unit_response_buffer_full() => {
                     let fetch = self.response_fifo.pop_front().unwrap();
                     log::debug!("accepted ldst unit fetch {}", fetch);
                     // m_memory_stats->memlatstat_read_done(mf);
-                    core.accept_ldst_unit_response(fetch);
+                    core.accept_ldst_unit_response(fetch, cycle);
                 }
                 _ => {
                     log::debug!("ldst unit fetch {} NOT YET ACCEPTED", fetch);
@@ -154,9 +150,7 @@ where
             "{}",
             style(format!(
                 "cycle {:02} cluster {}: got fetch from interconn: {}",
-                self.cycle.get(),
-                self.cluster_id,
-                fetch,
+                cycle, self.cluster_id, fetch,
             ))
             .cyan()
         );

src/config/mod.rs

@@ -317,7 +317,7 @@ pub enum Parallelization {
     Serial,
     RayonDeterministic,
     Deterministic,
-    Nondeterministic(u64),
+    Nondeterministic(usize),
 }
 
 #[allow(clippy::struct_excessive_bools)]