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rename translated address to physical address
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@romnn
romnn committed Sep 7, 2023
1 parent 06ac340 commit 9eac2c9
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Showing 9 changed files with 67 additions and 98 deletions.
31 changes: 9 additions & 22 deletions src/cache/data.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -242,36 +242,27 @@ where
}
.build();

let mut tlx_addr = self
// .inner
let mut physical_addr = self
.mem_controller
.to_physical_address(writeback_access.addr);

// the evicted block may have wrong chip id when
// advanced L2 hashing is used, so set the right chip
// address from the original mf
tlx_addr.chip = fetch.tlx_addr.chip;
tlx_addr.sub_partition = fetch.tlx_addr.sub_partition;
physical_addr.chip = fetch.physical_addr.chip;
physical_addr.sub_partition = fetch.physical_addr.sub_partition;

let partition_addr = self
// .inner
.mem_controller
.memory_partition_address(writeback_access.addr);

let writeback_fetch = mem_fetch::Builder {
instr: fetch.instr.clone(),
access: writeback_access,
// &self.inner.config,
// control_size: if is_write {
// mem_fetch::WRITE_PACKET_SIZE
// } else {
// mem_fetch::READ_PACKET_SIZE
// }
// .into(),
warp_id: 0,
core_id: 0,
cluster_id: 0,
tlx_addr,
physical_addr,
partition_addr,
}
.build();
Expand Down Expand Up @@ -392,12 +383,8 @@ where
}
.build();

let tlx_addr = self
// .inner
.mem_controller
.to_physical_address(new_access.addr);
let physical_addr = self.mem_controller.to_physical_address(new_access.addr);
let partition_addr = self
// .inner
.mem_controller
.memory_partition_address(new_access.addr);

Expand All @@ -407,7 +394,7 @@ where
warp_id: fetch.warp_id,
core_id: fetch.core_id,
cluster_id: fetch.cluster_id,
tlx_addr,
physical_addr,
partition_addr,
}
.build();
Expand Down Expand Up @@ -468,8 +455,8 @@ where
// .inner
.mem_controller
.to_physical_address(writeback_access.addr);
tlx_addr.chip = fetch.tlx_addr.chip;
tlx_addr.sub_partition = fetch.tlx_addr.sub_partition;
tlx_addr.chip = fetch.physical_addr.chip;
tlx_addr.sub_partition = fetch.physical_addr.sub_partition;

let partition_addr = self
.mem_controller
Expand All @@ -481,7 +468,7 @@ where
warp_id: 0,
core_id: 0,
cluster_id: 0,
tlx_addr,
physical_addr,
partition_addr,
}
.build();
Expand Down
6 changes: 2 additions & 4 deletions src/core.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1452,7 +1452,7 @@ where
}
.build();

let tlx_addr = self
let physical_addr = self
.config
.address_mapping()
.to_physical_address(access.addr);
Expand All @@ -1464,12 +1464,10 @@ where
let fetch = mem_fetch::Builder {
instr: None,
access,
// &self.config,
// mem_fetch::READ_PACKET_SIZE.into(),
warp_id,
core_id: self.core_id,
cluster_id: self.cluster_id,
tlx_addr,
physical_addr,
partition_addr,
}
.build();
Expand Down
4 changes: 2 additions & 2 deletions src/dram.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,8 @@ impl DRAM {
/// Here, we do nothing except logging statistics
/// see: `memory_stats_t::memlatstat_dram_access`()
pub fn access(&mut self, fetch: &mem_fetch::MemFetch) {
let dram_id = fetch.tlx_addr.chip as usize;
let bank = fetch.tlx_addr.bk as usize;
let dram_id = fetch.physical_addr.chip as usize;
let bank = fetch.physical_addr.bk as usize;

let mut stats = self.stats.lock();
let atom_size = self.config.atom_size;
Expand Down
33 changes: 7 additions & 26 deletions src/func_unit/load_store.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,6 @@ use std::collections::{HashMap, VecDeque};
use strum::EnumCount;

#[allow(clippy::module_name_repetitions)]
// pub struct LoadStoreUnit<I> {
pub struct LoadStoreUnit {
core_id: usize,
cluster_id: usize,
Expand All @@ -28,9 +27,6 @@ pub struct LoadStoreUnit {
next_global: Option<MemFetch>,
pub pending_writes: HashMap<usize, HashMap<u32, usize>>,
l1_latency_queue: Vec<Vec<Option<mem_fetch::MemFetch>>>,
// #[allow(dead_code)]
// interconn: Arc<dyn ic::Interconnect<ic::Packet<mem_fetch::MemFetch>>>,
// fetch_interconn: Arc<I>,
pub mem_port: ic::Port<mem_fetch::MemFetch>,
inner: fu::PipelinedSimdUnit,

Expand All @@ -41,14 +37,12 @@ pub struct LoadStoreUnit {
num_writeback_clients: usize,
}

// impl<I> std::fmt::Display for LoadStoreUnit<I> {
impl std::fmt::Display for LoadStoreUnit {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
write!(f, "{}", self.inner.name)
}
}

// impl<I> std::fmt::Debug for LoadStoreUnit<I> {
impl std::fmt::Debug for LoadStoreUnit {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
f.debug_struct(&self.inner.name)
Expand Down Expand Up @@ -81,7 +75,6 @@ enum MemStageAccessKind {
L_MEM_LD,
G_MEM_ST,
L_MEM_ST,
// N_MEM_STAGE_ACCESS_TYPE
}

#[derive(strum::EnumCount, strum::FromRepr, Hash, PartialEq, Eq, Clone, Copy, Debug)]
Expand All @@ -99,18 +92,12 @@ enum MemStageStallKind {
WB_CACHE_RSRV_FAIL,
}

impl LoadStoreUnit
// impl<I> LoadStoreUnit<I>
// where
// I: ic::MemFetchInterface + 'static,
{
impl LoadStoreUnit {
pub fn new(
id: usize,
core_id: usize,
cluster_id: usize,
warps: Vec<warp::Ref>,
// interconn: Arc<dyn ic::Interconnect<ic::Packet<mem_fetch::MemFetch>>>,
// fetch_interconn: Arc<I>,
mem_port: ic::Port<mem_fetch::MemFetch>,
operand_collector: Arc<Mutex<opcoll::RegisterFileUnit>>,
scoreboard: Arc<RwLock<Scoreboard>>,
Expand Down Expand Up @@ -628,7 +615,7 @@ impl LoadStoreUnit
let instr = self.inner.dispatch_reg.as_mut().unwrap();
let access = instr.mem_access_queue.pop_back().unwrap();

let tlx_addr = self
let physical_addr = self
.config
.address_mapping()
.to_physical_address(access.addr);
Expand All @@ -643,7 +630,7 @@ impl LoadStoreUnit
warp_id: instr.warp_id,
core_id: self.core_id,
cluster_id: self.cluster_id,
tlx_addr,
physical_addr,
partition_addr,
}
.build();
Expand Down Expand Up @@ -737,10 +724,7 @@ impl LoadStoreUnit
let is_store = instr.is_store();
let access = instr.mem_access_queue.pop_back().unwrap();

// let tlx_addr = crate::mcu::TranslatedAddress::default();
// let partition_addr = 0;

let tlx_addr = self
let physical_addr = self
.config
.address_mapping()
.to_physical_address(access.addr);
Expand All @@ -755,7 +739,7 @@ impl LoadStoreUnit
warp_id: instr.warp_id,
core_id: self.core_id,
cluster_id: self.cluster_id,
tlx_addr,
physical_addr,
partition_addr,
}
.build();
Expand Down Expand Up @@ -794,10 +778,7 @@ impl LoadStoreUnit
);
stall_cond
} else {
// let tlx_addr = crate::mcu::TranslatedAddress::default();
// let partition_addr = 0;

let tlx_addr = self
let physical_addr = self
.config
.address_mapping()
.to_physical_address(access.addr);
Expand All @@ -813,7 +794,7 @@ impl LoadStoreUnit
warp_id: instr.warp_id,
core_id: self.core_id,
cluster_id: self.cluster_id,
tlx_addr,
physical_addr,
partition_addr,
}
.build();
Expand Down
42 changes: 21 additions & 21 deletions src/mcu.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -320,7 +320,7 @@ pub trait MemoryController: std::fmt::Debug + Send + Sync + 'static {

/// Compute the physical address for a virtual address.
#[must_use]
fn to_physical_address(&self, addr: address) -> TranslatedAddress;
fn to_physical_address(&self, addr: address) -> PhysicalAddress;

/// The number of memory partitions connected to the memory controller
#[must_use]
Expand Down Expand Up @@ -351,8 +351,8 @@ impl MemoryController for MemoryControllerUnit {
}

#[inline]
fn to_physical_address(&self, addr: address) -> TranslatedAddress {
let mut tlx = TranslatedAddress::default();
fn to_physical_address(&self, addr: address) -> PhysicalAddress {
let mut tlx = PhysicalAddress::default();
let num_channels = self.num_channels as u64;

let dec = &self.decode_config;
Expand Down Expand Up @@ -431,7 +431,7 @@ fn packbits(mask: super::address, val: super::address, low: u8, high: u8) -> sup
}

#[derive(Default, Debug, Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct TranslatedAddress {
pub struct PhysicalAddress {
pub bk: u64,
pub chip: u64,
pub row: u64,
Expand All @@ -440,7 +440,7 @@ pub struct TranslatedAddress {
pub sub_partition: u64,
}

impl std::hash::Hash for TranslatedAddress {
impl std::hash::Hash for PhysicalAddress {
fn hash<H: std::hash::Hasher>(&self, state: &mut H) {
self.bk.hash(state);
self.chip.hash(state);
Expand All @@ -460,7 +460,7 @@ mod tests {
format!("{n:064b}")
}

impl From<playground::addrdec::AddrDec> for super::TranslatedAddress {
impl From<playground::addrdec::AddrDec> for super::PhysicalAddress {
fn from(addr: playground::addrdec::AddrDec) -> Self {
Self {
chip: u64::from(addr.chip),
Expand All @@ -473,18 +473,18 @@ mod tests {
}
}

fn compute_tlx(
fn compute_physical_addr(
config: &config::GPU,
addr: u64,
) -> (super::TranslatedAddress, super::TranslatedAddress) {
) -> (super::PhysicalAddress, super::PhysicalAddress) {
let mapping = config.address_mapping();
let ref_mapping = playground::addrdec::AddressTranslation::new(
config.num_memory_controllers as u32,
config.num_sub_partition_per_memory_channel as u32,
);
(
mapping.to_physical_address(addr),
super::TranslatedAddress::from(ref_mapping.tlx(addr)),
super::PhysicalAddress::from(ref_mapping.tlx(addr)),
)
}

Expand Down Expand Up @@ -572,59 +572,59 @@ mod tests {
}

#[test]
fn test_tlx_sub_partition_gtx1080() {
fn test_physical_addr_sub_partition_gtx1080() {
let config = config::GPU {
num_memory_controllers: 8,
num_sub_partition_per_memory_channel: 2,
..config::GPU::default()
};

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_064_896);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_064_896);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 0);
assert_eq!(tlx_addr.sub_partition, 0);

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_065_024);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_065_024);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 1);
assert_eq!(tlx_addr.sub_partition, 1);

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_065_120);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_065_120);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 1);
assert_eq!(tlx_addr.sub_partition, 1);

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_065_152);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_065_152);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 2);
assert_eq!(tlx_addr.sub_partition, 2);

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_065_472);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_065_472);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 4);
assert_eq!(tlx_addr.sub_partition, 4);

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_066_048);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_066_048);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 9);
assert_eq!(tlx_addr.sub_partition, 9);

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_066_432);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_066_432);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 12);
assert_eq!(tlx_addr.sub_partition, 12);

let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 140_159_034_066_944);
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 140_159_034_066_944);
dbg!(&tlx_addr, &ref_tlx_addr);
assert_eq!(ref_tlx_addr.sub_partition, 0);
assert_eq!(tlx_addr.sub_partition, 0);
}

#[test]
fn test_tlx() {
fn test_physical_addr() {
let config = config::GPU::default();
let (tlx_addr, ref_tlx_addr) = compute_tlx(&config, 139_823_420_539_008);
let want = super::TranslatedAddress {
let (tlx_addr, ref_tlx_addr) = compute_physical_addr(&config, 139_823_420_539_008);
let want = super::PhysicalAddress {
chip: 0,
bk: 1,
row: 2900,
Expand Down
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