refactor

- remove stats generic from cache trait - replace &dyn Trait dynamic dispatch for generics where possible - remove warp instruction generic from scoreboard trait - avoid allocations in generate memory accesses for instruction
romnn · Feb 6, 2024 · 6f5f838 · 6f5f838
1 parent 8acb3ab
commit 6f5f838
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Showing 26 changed files with 955 additions and 778 deletions.
diff --git a/src/arbitration.rs b/src/arbitration.rs
@@ -64,7 +64,7 @@ impl ArbitrationUnit {
     }
 }
 
-pub trait Arbiter: std::fmt::Debug + Send + Sync + 'static {
+pub trait Arbitrate: std::fmt::Debug + Send + Sync + 'static {
     fn as_any(&self) -> &dyn std::any::Any;
 
     /// Check if a subpartition still has credit
@@ -82,7 +82,7 @@ pub trait Arbiter: std::fmt::Debug + Send + Sync + 'static {
     fn last_borrower(&self) -> usize;
 }
 
-impl Arbiter for ArbitrationUnit {
+impl Arbitrate for ArbitrationUnit {
     // #[inline]
     fn as_any(&self) -> &dyn std::any::Any {
         self

diff --git a/src/cache/base.rs b/src/cache/base.rs
@@ -47,7 +47,7 @@ pub enum Kind {
 /// Implements common functions for `read_only_cache` and `data_cache`
 /// Each subclass implements its own 'access' function
 #[derive()]
-pub struct Base<B, CC, S> {
+pub struct Base<B, CC> {
     /// Name of the cache
     pub name: String,
     /// ID of the cache
@@ -60,7 +60,7 @@ pub struct Base<B, CC, S> {
     // Is L1 cache
     // pub is_l1: bool,
     // pub stats: Arc<Mutex<S>>,
-    pub stats: S,
+    pub stats: stats::cache::PerKernel,
     pub cache_controller: CC,
     pub cache_config: cache::Config,
 
@@ -76,23 +76,21 @@ pub struct Base<B, CC, S> {
 }
 
 #[derive(Debug, Clone)]
-pub struct Builder<CC, S> {
+pub struct Builder<CC> {
     pub name: String,
     pub id: usize,
     pub kind: Kind,
-    // pub stats: Arc<Mutex<S>>,
-    pub stats: S,
     pub cache_controller: CC,
     pub cache_config: Arc<config::Cache>,
     pub accelsim_compat: bool,
 }
 
-impl<CC, S> Builder<CC, S>
+impl<CC> Builder<CC>
 where
     CC: Clone,
 {
     #[must_use]
-    pub fn build<B>(self) -> Base<B, CC, S>
+    pub fn build<B>(self) -> Base<B, CC>
     where
         B: cache::block::Block,
     {
@@ -119,16 +117,17 @@ where
 
         // let is_l1 = self.name.to_uppercase().contains("L1D");
 
-        // stats::cache::PerKernel
+        let stats = stats::cache::PerKernel::default();
+
         Base {
             name: self.name,
             id: self.id,
             kind: self.kind,
             // is_l1,
             tag_array,
             mshrs,
+            stats,
             // top_port: None,
-            stats: self.stats,
             cache_config,
             cache_controller: self.cache_controller,
             bandwidth,
@@ -139,7 +138,7 @@ where
     }
 }
 
-impl<B, CC> Base<B, CC, stats::cache::PerKernel>
+impl<B, CC> Base<B, CC>
 where
     CC: cache::CacheController,
     B: cache::block::Block,
@@ -344,7 +343,7 @@ where
 }
 
 // impl<B, CC, S> crate::engine::cycle::Component for Base<B, CC, S> {
-impl<B, CC, S> Base<B, CC, S> {
+impl<B, CC> Base<B, CC> {
     /// Sends next request to top memory in the memory hierarchy.
     pub fn cycle(
         &mut self,
@@ -396,7 +395,7 @@ impl<B, CC, S> Base<B, CC, S> {
     }
 }
 
-impl<B, CC, S> Base<B, CC, S> {
+impl<B, CC> Base<B, CC> {
     /// Checks whether this request can be handled in this cycle.
     ///
     /// `n` equals the number of misses to be handled in this cycle.
@@ -453,7 +452,7 @@ impl<B, CC, S> Base<B, CC, S> {
     // }
 }
 
-impl<B, CC, S> Base<B, CC, S>
+impl<B, CC> Base<B, CC>
 where
     CC: cache::CacheController,
     B: cache::block::Block,
@@ -715,7 +714,7 @@ where
     }
 }
 
-impl<B, CC, S> super::Bandwidth for Base<B, CC, S> {
+impl<B, CC> super::Bandwidth for Base<B, CC> {
     fn has_free_data_port(&self) -> bool {
         self.bandwidth.has_free_data_port()
     }

diff --git a/src/cache/data.rs b/src/cache/data.rs
@@ -13,14 +13,12 @@ use std::collections::VecDeque;
 use tag_array::Access;
 
 #[derive(Clone)]
-pub struct Builder<MC, CC, S> {
+pub struct Builder<MC, CC> {
     // pub struct Builder<CC, S> {
     pub name: String,
     /// SM ID or subpartition ID depending on cache type
     pub id: usize,
     pub kind: cache::base::Kind,
-    // pub stats: Arc<Mutex<S>>,
-    pub stats: S,
     // pub mem_controller: Arc<dyn mcu::MemoryController>,
     pub mem_controller: Arc<MC>,
     pub cache_controller: CC,
@@ -35,9 +33,9 @@ pub struct Builder<MC, CC, S> {
 /// The cache uses a write-evict (global) or write-back (local) policy
 /// at the granularity of individual blocks.
 /// (the policy used in fermi according to the CUDA manual)
-pub struct Data<MC, CC, S> {
+pub struct Data<MC, CC> {
     // pub struct Data<CC, S> {
-    pub inner: cache::base::Base<cache::block::sector::Block<NUM_SECTORS>, CC, S>,
+    pub inner: cache::base::Base<cache::block::sector::Block<NUM_SECTORS>, CC>,
 
     /// Memory controller
     // pub mem_controller: Arc<dyn mcu::MemoryController>,
@@ -48,16 +46,15 @@ pub struct Data<MC, CC, S> {
     write_back_type: AccessKind,
 }
 
-impl<MC, CC, S> Builder<MC, CC, S>
+impl<MC, CC> Builder<MC, CC>
 where
     CC: Clone,
 {
-    pub fn build(self) -> Data<MC, CC, S> {
+    pub fn build(self) -> Data<MC, CC> {
         let inner = super::base::Builder {
             name: self.name,
             id: self.id,
             kind: self.kind,
-            stats: self.stats,
             cache_controller: self.cache_controller,
             cache_config: self.cache_config,
             accelsim_compat: self.config.accelsim_compat,
@@ -72,7 +69,7 @@ where
     }
 }
 
-impl<MC, CC, S> Data<MC, CC, S> {
+impl<MC, CC> Data<MC, CC> {
     // impl<CC, S> Data<CC, S> {
     // #[inline]
     // pub fn set_top_port(&mut self, port: ic::Port<mem_fetch::MemFetch>) {
@@ -82,7 +79,7 @@ impl<MC, CC, S> Data<MC, CC, S> {
     // }
 }
 
-impl<MC, CC> Data<MC, CC, stats::cache::PerKernel>
+impl<MC, CC> Data<MC, CC>
 // impl<CC> Data<CC, stats::cache::PerKernel>
 where
     MC: crate::mcu::MemoryController,
@@ -702,7 +699,7 @@ where
     }
 }
 
-impl<MC, CC> Data<MC, CC, stats::cache::PerKernel>
+impl<MC, CC> Data<MC, CC>
 where
     CC: cache::CacheController,
 {
@@ -957,7 +954,7 @@ where
 //     }
 // }
 
-impl<MC, CC> cache::Cache<stats::cache::PerKernel> for Data<MC, CC, stats::cache::PerKernel>
+impl<MC, CC> cache::Cache for Data<MC, CC>
 // impl<CC> cache::Cache<stats::cache::PerKernel> for Data<CC, stats::cache::PerKernel>
 where
     MC: crate::mcu::MemoryController,
@@ -979,15 +976,6 @@ where
     //     self.inner.top_port.as_deref_mut()
     // }
 
-    // fn per_kernel_stats(&self) -> &Arc<Mutex<stats::cache::PerKernel>> {
-    fn per_kernel_stats(&self) -> &stats::cache::PerKernel {
-        &self.inner.stats
-    }
-
-    fn per_kernel_stats_mut(&mut self) -> &mut stats::cache::PerKernel {
-        &mut self.inner.stats
-    }
-
     fn controller(&self) -> &dyn cache::CacheController {
         &self.inner.cache_controller
     }
@@ -1210,7 +1198,18 @@ where
     }
 }
 
-impl<MC, CC, S> cache::Bandwidth for Data<MC, CC, S> {
+impl<MC, CC> cache::ComputeStats for Data<MC, CC> {
+    // fn per_kernel_stats(&self) -> &Arc<Mutex<stats::cache::PerKernel>> {
+    fn per_kernel_stats(&self) -> &stats::cache::PerKernel {
+        &self.inner.stats
+    }
+
+    fn per_kernel_stats_mut(&mut self) -> &mut stats::cache::PerKernel {
+        &mut self.inner.stats
+    }
+}
+
+impl<MC, CC> cache::Bandwidth for Data<MC, CC> {
     // impl<CC, S> cache::Bandwidth for Data<CC, S> {
     fn has_free_data_port(&self) -> bool {
         self.inner.has_free_data_port()

diff --git a/src/cache/l2.rs b/src/cache/l2.rs
@@ -155,7 +155,7 @@ where
 #[allow(clippy::module_name_repetitions)]
 pub struct DataL2<MC> {
     pub cache_config: Arc<config::L2DCache>,
-    pub inner: super::data::Data<MC, L2DataCacheController<MC>, stats::cache::PerKernel>,
+    pub inner: super::data::Data<MC, L2DataCacheController<MC>>,
 }
 
 impl<MC> DataL2<MC>
@@ -174,12 +174,10 @@ where
             mem_controller.clone(),
             config.accelsim_compat,
         );
-        let stats = stats::cache::PerKernel::default();
         let inner = super::data::Builder {
             name,
             id: sub_partition_id,
             kind: cache::base::Kind::OffChip,
-            stats,
             config,
             cache_controller,
             mem_controller,
@@ -208,7 +206,7 @@ impl<MC> DataL2<MC> {
 //     }
 // }
 
-impl<MC> super::Cache<stats::cache::PerKernel> for DataL2<MC>
+impl<MC> super::Cache for DataL2<MC>
 where
     MC: crate::mcu::MemoryController,
 {
@@ -229,15 +227,6 @@ where
         self
     }
 
-    // #[inline]
-    fn per_kernel_stats(&self) -> &stats::cache::PerKernel {
-        &self.inner.inner.stats
-    }
-
-    fn per_kernel_stats_mut(&mut self) -> &mut stats::cache::PerKernel {
-        &mut self.inner.inner.stats
-    }
-
     fn controller(&self) -> &dyn cache::CacheController {
         &self.inner.inner.cache_controller
     }
@@ -326,6 +315,16 @@ where
     }
 }
 
+impl<MC> cache::ComputeStats for DataL2<MC> {
+    fn per_kernel_stats(&self) -> &stats::cache::PerKernel {
+        &self.inner.inner.stats
+    }
+
+    fn per_kernel_stats_mut(&mut self) -> &mut stats::cache::PerKernel {
+        &mut self.inner.inner.stats
+    }
+}
+
 impl<MC> super::Bandwidth for DataL2<MC> {
     fn has_free_data_port(&self) -> bool {
         self.inner.has_free_data_port()

diff --git a/src/cache/mod.rs b/src/cache/mod.rs
@@ -135,7 +135,7 @@ pub fn select_status(probe: RequestStatus, access: RequestStatus) -> RequestStat
 }
 
 // pub trait Cache<S>: crate::engine::cycle::Component + Send + Sync + Bandwidth + 'static {
-pub trait Cache<S>: Send + Sync + Bandwidth + 'static {
+pub trait Cache: Send + Sync + Bandwidth + 'static {
     fn cycle(
         &mut self,
         top_port: &mut dyn ic::Connection<ic::Packet<mem_fetch::MemFetch>>,
@@ -148,13 +148,6 @@ pub trait Cache<S>: Send + Sync + Bandwidth + 'static {
     /// Get top port
     // fn top_port(&mut self) -> Option<&mut dyn ic::Connection<ic::Packet<mem_fetch::MemFetch>>>;
 
-    /// Per-kenrel cache statistics.
-    fn per_kernel_stats(&self) -> &S;
-
-    /// Per-kenrel cache statistics.
-    fn per_kernel_stats_mut(&mut self) -> &mut S;
-    // fn per_kernel_stats(&self) -> &Arc<Mutex<S>>;
-
     /// Cache controller
     fn controller(&self) -> &dyn CacheController;
 
@@ -235,3 +228,12 @@ pub trait Bandwidth {
 
     fn has_free_fill_port(&self) -> bool;
 }
+
+pub trait ComputeStats {
+    /// Per-kenrel cache statistics.
+    fn per_kernel_stats(&self) -> &stats::cache::PerKernel;
+
+    /// Per-kenrel cache statistics.
+    fn per_kernel_stats_mut(&mut self) -> &mut stats::cache::PerKernel;
+    // fn per_kernel_stats(&self) -> &Arc<Mutex<S>>;
+}