clock subsystem works for all devboards

rodan · Nov 12, 2021 · b44da99 · b44da99
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diff --git a/README.md b/README.md
@@ -1,6 +1,8 @@
 
 ## reference libraries for msp430
 
+/\/\/\/\/\/\/\/\/\/\/\/ UNDER DEVELOPMENT /\/\/\/\/\/\/\/\/\/\/\/
+
 this library provides a glue layer between the upstream [Texas Instruments mspdriverlib](https://www.ti.com/tool/MSPDRIVERLIB) and projects that need quick prototyping while also allowing easier code migration from one msp430 microcontroller to another. on one hand it has a number of generic functions and configurable compile-time defines that will set up the hardware abstraction layer allowing the user to focus on the higher level code and on the other hand it can be out-of-the-way and allow direct access to the registers or to the TI driverlib.
 
 
@@ -116,8 +118,8 @@ tests of the library are performed on the following target devices:
 
 microcontroller | family       |clock|uart | i2c | spi | scheduling
 --------------- | ------------ | --- | --- | --- | --- | ----------
-CC430F5137   | MSP430F5xx_6xx  | [ ] | [ ] | [ ] | [ ] | [ ]
-MSP430F5438  | MSP430F5xx_6xx  | [ ] | [ ] | [ ] | [ ] | [ ]
+CC430F5137   | MSP430F5xx_6xx  | [x] | [ ] | [ ] | [ ] | [ ]
+MSP430F5438  | MSP430F5xx_6xx  | [x] | [ ] | [ ] | [ ] | [ ]
 MSP430F5510  | MSP430F5xx_6xx  | [x] | [x] | [x] | [x] | [ ]
 MSP430F5529  | MSP430F5xx_6xx  | [x] | [ ] | [ ] | [ ] | [ ]
 MSP430FR2355 | MSP430FR2xx_4xx | [x] | [ ] | [ ] | [ ] | [ ]

diff --git a/glue/MSP430F5xx_6xx/clock.c b/glue/MSP430F5xx_6xx/clock.c
@@ -12,7 +12,9 @@
 void clock_port_init(void)
 {
 #ifdef USE_XT1
-    #if defined (__MSP430F5510__) || defined (__MSP430F5529__)
+    #if defined (__CC430F5137__) 
+        P5SEL |= BIT0 | BIT1;
+    #elif defined (__MSP430F5510__) || defined (__MSP430F5529__)
         P5SEL |= BIT4 | BIT5;
     #elif defined (__MSP430F5438__)
         P7SEL |= BIT0 | BIT1;
@@ -72,7 +74,11 @@ void clock_init(void)
 
     // turn on 
 #ifdef USE_XT1
+    #if defined (__CC430F5137__)
+    UCS_turnOnLFXT1WithTimeout(CLK_LFXT_DRIVE, UCS_XCAP_0, 30000);
+    #else
     UCS_turnOnLFXT1(CLK_LFXT_DRIVE, UCS_XCAP_0);
+    #endif
 #endif
 
 #ifdef USE_XT2

diff --git a/glue/MSP430F5xx_6xx/clock.h b/glue/MSP430F5xx_6xx/clock.h
@@ -6,7 +6,9 @@ extern "C" {
 #endif
 
 #define       ACLK_FREQ  32768
+#ifndef CLK_LFXT_DRIVE
 #define  CLK_LFXT_DRIVE  UCS_XT1_DRIVE_0
+#endif
 
 void clock_port_init(void);
 void clock_init(void);

diff --git a/glue/MSP430F5xx_6xx/clock_selection.h b/glue/MSP430F5xx_6xx/clock_selection.h
@@ -37,6 +37,12 @@ extern "C" {
     #error SMCLK_FREQ_xM not defined in config.h
 #endif
 
+#if SMCLK_FREQ > 20000000
+    #if defined (__CC430F5137__)
+    #error "unsupported clock frequency for this IC"
+    #endif
+#endif
+
 #if SMCLK_FREQ > 25000000
     #if defined (__MSP430F5529__)
     #error "unsupported clock frequency for this IC"

diff --git a/glue/MSP430F5xx_6xx/msp430_hal.c b/glue/MSP430F5xx_6xx/msp430_hal.c
@@ -10,15 +10,16 @@
 
 void msp430_hal_init(const uint8_t gpio_flags)
 {
+
     uint8_t dir = 0; // by default the pin is floating
     uint8_t out = 0; // default logic level is low if pin is output
 
     if (gpio_flags & HAL_GPIO_DIR_OUTPUT) {
-        dir = 1;
+        dir = 0xff;
     }
 
     if (gpio_flags & HAL_GPIO_OUT_HIGH) {
-        out = 1;
+        out = 0xff;
     }
 
     // Turn everything off, device drivers enable what is needed.
@@ -57,7 +58,6 @@ void msp430_hal_init(const uint8_t gpio_flags)
     P11SEL = 0;
 #endif
 
-    // make all gpios inputs
 #ifdef __MSP430_HAS_PORT1_R__
     P1DIR = dir;
     P1OUT = out;
@@ -102,4 +102,5 @@ void msp430_hal_init(const uint8_t gpio_flags)
     P11DIR = dir;
     P11OUT = out;
 #endif
+
 }
diff --git a/glue/MSP430FR2xx_4xx/clock.h b/glue/MSP430FR2xx_4xx/clock.h
@@ -6,7 +6,9 @@ extern "C" {
 #endif
 
 #define       ACLK_FREQ  32768
+#ifndef CLK_LFXT_DRIVE
 #define  CLK_LFXT_DRIVE  CS_XT1_DRIVE_0
+#endif
 
 void clock_port_init(void);
 void clock_init(void);

diff --git a/glue/MSP430FR2xx_4xx/msp430_hal.c b/glue/MSP430FR2xx_4xx/msp430_hal.c
@@ -14,11 +14,11 @@ void msp430_hal_init(const uint8_t gpio_flags)
     uint8_t out = 0; // default logic level is low if pin is output
 
     if (gpio_flags & HAL_GPIO_DIR_OUTPUT) {
-        dir = 1;
+        dir = 0xff;
     }
 
     if (gpio_flags & HAL_GPIO_OUT_HIGH) {
-        out = 1;
+        out = 0xff;
     }
 
     // Turn everything off, device drivers enable what is needed.
@@ -57,7 +57,6 @@ void msp430_hal_init(const uint8_t gpio_flags)
     P11SEL = 0;
 #endif
 
-    // make all gpios inputs
 #ifdef __MSP430_HAS_PORT1_R__
     P1DIR = dir;
     P1OUT = out;

diff --git a/glue/MSP430FR5xx_6xx/clock.h b/glue/MSP430FR5xx_6xx/clock.h
@@ -6,7 +6,9 @@ extern "C" {
 #endif
 
 #define       ACLK_FREQ  32768
+#ifndef CLK_LFXT_DRIVE
 #define  CLK_LFXT_DRIVE  CS_LFXT_DRIVE_0
+#endif
 
 void clock_port_init(void);
 void clock_init(void);

diff --git a/glue/MSP430FR5xx_6xx/msp430_hal.c b/glue/MSP430FR5xx_6xx/msp430_hal.c
@@ -14,11 +14,11 @@ void msp430_hal_init(const uint8_t gpio_flags)
     uint8_t out = 0; // default logic level is low if pin is output
 
     if (gpio_flags & HAL_GPIO_DIR_OUTPUT) {
-        dir = 1;
+        dir = 0xff;
     }
 
     if (gpio_flags & HAL_GPIO_OUT_HIGH) {
-        out = 1;
+        out = 0xff;
     }
 
     // Turn everything off, device drivers enable what is needed.
@@ -57,7 +57,6 @@ void msp430_hal_init(const uint8_t gpio_flags)
     P11SEL1 = 0;
 #endif
 
-    // make all gpios inputs
 #ifdef __MSP430_HAS_PORT1_R__
     P1DIR = dir;
     P1OUT = out;

diff --git a/tests/clock_system/config.h b/tests/clock_system/config.h
@@ -1,11 +1,11 @@
 #ifndef _CONFIG_H_
 #define _CONFIG_H_
 
-#define USE_XT1
+//#define USE_XT1
 //#define USE_XT2
 
-#define SMCLK_FREQ_1M
-//#define SMCLK_FREQ_4M
+//#define SMCLK_FREQ_1M
+#define SMCLK_FREQ_4M
 //#define SMCLK_FREQ_8M
 //#define SMCLK_FREQ_16M
 //#define SMCLK_FREQ_24M

diff --git a/tests/clock_system/main.c b/tests/clock_system/main.c
@@ -19,7 +19,10 @@ int main(void)
     clock_init();
 
     // output SMCLK on a pin
-#if defined (__MSP430FR5994__) || ((__MSP430FR5969__))
+#if defined (__CC430F5137__)
+    P3DIR |= BIT7;
+    P3SEL |= BIT7;
+#elif defined (__MSP430FR5994__) || ((__MSP430FR5969__))
     P3DIR |= BIT4;
     P3SEL1 |= BIT4;
 #elif defined (__MSP430FR2355__)
@@ -38,6 +41,9 @@ int main(void)
     //P10DIR |= BIT0;
     //P10SEL0 |= BIT0;
     //P10SEL1 |= BIT0;
+#elif defined (__MSP430F5438__)
+    P11DIR |= BIT2;
+    P11SEL |= BIT2;
 #elif defined (__MSP430F5510__) || (__MSP430F5529__)
     P2DIR |= BIT2;
     P2SEL |= BIT2;

diff --git a/tests/clock_system/proj.h b/tests/clock_system/proj.h
@@ -3,13 +3,24 @@
 
 #include <msp430.h>
 
+#if defined (__MSP430F5438__)
+#define sig0_on              P10OUT |= BIT6
+#define sig0_off             P10OUT &= ~BIT6
+#define sig0_switch          P10OUT ^= BIT6
+
+#define sig1_on              P10OUT |= BIT7
+#define sig1_off             P10OUT &= ~BIT7
+#define sig1_switch          P10OUT ^= BIT7
+
+#else
 #define sig0_on              P1OUT |= BIT0
 #define sig0_off             P1OUT &= ~BIT0
 #define sig0_switch          P1OUT ^= BIT0
 
 #define sig1_on              P1OUT |= BIT1
 #define sig1_off             P1OUT &= ~BIT1
 #define sig1_switch          P1OUT ^= BIT1
+#endif
 
 #define sig2_on              P1OUT |= BIT3
 #define sig2_off             P1OUT &= ~BIT3

diff --git a/tests/clock_system/version.h b/tests/clock_system/version.h
@@ -1,9 +1,9 @@
 #ifndef __VERSION_H__
 #define __VERSION_H__
 
-// compiled on Fri Nov 12 09:45:57 UTC 2021
+// compiled on Fri Nov 12 13:55:48 UTC 2021
 
-#define BUILD 86
-#define COMMIT 81
+#define BUILD 135
+#define COMMIT 82
 
 #endif