Fix WFI decoding bug and circular combinatorial in forwarding logic

robotman2412 · Dec 30, 2023 · 3af0802 · 3af0802
1 parent 0326bd9
commit 3af0802
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Showing 3 changed files with 12 additions and 11 deletions.
diff --git a/hdl/boa32_cpu.sv b/hdl/boa32_cpu.sv
@@ -340,7 +340,7 @@ module boa32_cpu#(
         fw_in_rs2_mem = fw_mem_rs2_mem_rd ? fw_out_mem : wb_rd_val;
 
         // Stalling logic.
-        if (is_xret && csr.we) begin
+        if (is_xret && st_mem.csr_we) begin
             // ID contains an MRET, which has a data dependency on CSRs.
             // Stall ID so that the current CSR write takes effect.
             fw_stall_id = 1;

diff --git a/hdl/stages/boa_stage_id.sv b/hdl/stages/boa_stage_id.sv
@@ -491,10 +491,10 @@ module boa_insn_validator#(
             // Privileged instructions.
             casez (insn[31:20])
                 default:            begin valid_system = 0;          legal_system = 1; end
-                12'b0000000_0000?:  begin valid_system = 1;          legal_system = 1; end
-                12'b0001000_00010:  begin valid_system = has_s_mode; legal_system = privilege[0]; end
-                12'b0011000_00010:  begin valid_system = 1;          legal_system = privilege[1]; end
-                12'b0011000_00101:  begin valid_system = 1;          legal_system = 1; end
+                12'b0000000_0000?:  begin valid_system = 1;          legal_system = 1; end // ECALL and EBREAK
+                12'b0001000_00010:  begin valid_system = has_s_mode; legal_system = privilege[0]; end // SRET
+                12'b0011000_00010:  begin valid_system = 1;          legal_system = privilege[1]; end // MRET
+                12'b0001000_00101:  begin valid_system = 1;          legal_system = 1; end // WFI
             endcase
         end else begin
             // CSR instructions.

diff --git a/hdl/stages/boa_stage_mem.sv b/hdl/stages/boa_stage_mem.sv
@@ -175,18 +175,19 @@ module boa_stage_mem(
             csr.wdata = 'bx;
         end
     end
-    logic  csr_re;
+    logic  csr_re, csr_we;
     always @(*) begin
-        if (d_valid && d_insn[6:2] == `RV_OP_SYSTEM && d_insn[14:12] != 2'b00) begin
+        if (d_insn[6:2] == `RV_OP_SYSTEM && d_insn[14:12] != 2'b00) begin
             // CSR instruction.
             csr_re = 1;
-            csr.we = d_insn[14] || (d_insn[19:15] != 0);
+            csr_we = d_insn[14] || (d_insn[19:15] != 0);
         end else begin
             // Not CSR instruction.
             csr_re = 0;
-            csr.we = 0;
+            csr_we = 0;
         end
     end
+    assign csr.we = d_valid && csr_we;
 
     logic       r_csr_re;
     logic[31:0] r_csr_rdata;
@@ -208,9 +209,9 @@ module boa_stage_mem(
             trap    <= mem_if.ealign;
             cause   <= mem_if.we ? `RV_ECAUSE_SALIGN : `RV_ECAUSE_LALIGN;
 
-        end else if ((csr_re && !csr.exists) || (csr.we && csr.rdonly)) begin
+        end else if ((csr_re && !csr.exists) || (csr_we && csr.rdonly)) begin
             // CSR access error.
-            trap    <= 1;
+            trap    <= d_valid;
             cause   <= `RV_ECAUSE_IILLEGAL;
 
         end else begin