update fence interaction

zacas.adoc

@@ -152,11 +152,6 @@ aligned for _quadwords_, eight-byte aligned for _doublewords_, and four-byte
 aligned for _words_). And the same exception options apply if the address
 is not naturally aligned.
 
-An `AMOCAS.W/D/Q` generates a memory read access and, if successful, generates
-a memory write access to store the _swap_ value. An unsuccessful `AMOCAS.W/D/Q`
-may either not perform a memory write or may write back the old value loaded
-from memory. An `AMOCAS.W/D/Q` instruction always requires write permissions.
-
 Just as for AMOs in the A extension, the `AMOCAS.W/D/Q` optionally provide
 release consistency semantics, using the `aq` and `rl` bits, to help implement
 multiprocessor synchronization. The memory operation performed by an
@@ -165,6 +160,18 @@ release semantics if `rl` bit is 1. The memory operation performed by an
 `AMOCAS.W/D/Q`, when not successful, has acquire semantics if `aq` bit is 1 but
 does not have release semantics, regardless of `rl`.
 
+A FENCE instruction may be used to order the memory read and, if produced, the
+memory write by an `AMOCAS.W/D/Q` instruction.
+
+[NOTE]
+====
+An unsuccessful `AMOCAS.W/D/Q` may either not perform a memory write or may
+write back the old value loaded from memory. The memory write, if produced, does
+not have release semantics, regardless of `rl`.
+====
+
+An `AMOCAS.W/D/Q` instruction always requires write permissions.
+
 <<<
 
 [NOTE]