Add missing pattern for v4qi and v8qi shift instruction

gcc/config/riscv/rvp.md

@@ -5467,18 +5467,16 @@
  }
 })
 
-(define_expand "riscv_<shift><mode>3"
- [(set (match_operand:VQI 0 "register_operand"  "")
- (any_shift:VQI (match_operand:VQI 1 "register_operand" "")
-  (match_operand:SI 2 "rimm3u_operand" "")))]
+(define_insn "*riscv_lshr<mode>3"
+ [(set (match_operand:VHI 0 "register_operand" "= r, r")
+ (lshiftrt:VHI (match_operand:VHI 1 "register_operand" " r, r")
+  (match_operand:SI 2  "rimm4u_operand" " u04, r")))]
  "TARGET_ZPN"
-{
- if (operands[2] == const0_rtx)
- {
- emit_move_insn (operands[0], operands[1]);
- DONE;
- }
-})
+ "@
+ srli16\t%0, %1, %2
+ srl16\t%0, %1, %2"
+ [(set_attr "type" "simd, simd")
+ (set_attr "mode" "<MODE>, <MODE>")])
 
 (define_insn "*riscv_ashl<mode>3"
  [(set (match_operand:VHI 0 "register_operand" "= r, r")
@@ -5491,22 +5489,6 @@
  [(set_attr "type" "simd, simd")
  (set_attr "mode" "<MODE>, <MODE>")])
 
-;; ashrv4qi3 for SRA[I]8 in RV32P
-;; ashrv8qi3 for SRA[I]8 in RV64P
-;; ashrv2hi3 for SRA[I]16 in RV32P
-;; ashrv4hi3 for SRA[I]16 in RV64P
-;; ashrv2si3 for SRA[I]32 (RV64P only)
-(define_insn "*riscv_ashr<mode>3"
- [(set (match_operand:VQI 0 "register_operand" "= r, r")
- (ashiftrt:VQI (match_operand:VQI 1 "register_operand" " r, r")
- (match_operand:SI 2 "rimm3u_operand" " u03, r")))]
- "TARGET_ZPN"
- "@
- srai8\t%0, %1, %2
- sra8\t%0, %1, %2"
- [(set_attr "type" "simd, simd")
- (set_attr "mode" "<MODE>, <MODE>")])
-
 (define_insn "*riscv_ashr<mode>3"
  [(set (match_operand:VHI 0 "register_operand" "= r, r")
  (ashiftrt:VHI (match_operand:VHI 1 "register_operand" " r, r")
@@ -5518,19 +5500,27 @@
  [(set_attr "type" "simd, simd")
  (set_attr "mode" "<MODE>, <MODE>")])
 
-;; lshrv4qi3 for SRL[I]8 in RV32P
-;; lshrv8qi3 for SRL[I]8 in RV64P
-;; lshrv2hi3 for SRL[I]16 in RV32P
-;; lshrv4hi3 for SRL[I]16 in RV64P
-;; lshrv2si3 for SRL[I]32 (RV64P only)
-(define_insn "*riscv_lshr<mode>3"
+(define_expand "riscv_<shift><mode>3"
+ [(set (match_operand:VQI 0 "register_operand" "")
+ (any_shift:VQI (match_operand:VQI 1 "register_operand" "")
+ (match_operand:SI 2 "rimm3u_operand" "")))]
+ "TARGET_ZPN"
+{
+ if (operands[2] == const0_rtx)
+ {
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+ }
+})
+
+(define_insn "*riscv_ashr<mode>3"
  [(set (match_operand:VQI 0 "register_operand" "= r, r")
- (lshiftrt:VQI (match_operand:VQI 1 "register_operand" " r, r")
+ (ashiftrt:VQI (match_operand:VQI 1 "register_operand" " r, r")
  (match_operand:SI 2 "rimm3u_operand" " u03, r")))]
  "TARGET_ZPN"
  "@
- srli8\t%0, %1, %2
- srl8\t%0, %1, %2"
+ srai8\t%0, %1, %2
+ sra8\t%0, %1, %2"
  [(set_attr "type" "simd, simd")
  (set_attr "mode" "<MODE>, <MODE>")])
 
@@ -5545,22 +5535,6 @@
  [(set_attr "type" "simd, simd")
  (set_attr "mode" "<MODE>, <MODE>")])
 
-;; ashlv4qi3 for SLL[I]8 in RV32P
-;; ashlv8qi3 for SLL[I]8 in RV64P
-;; ashlv2hi3 for SLL[I]16 in RV32P
-;; ashlv4hi3 for SLL[I]16 in RV64P
-;; ashlv2si3 for SLL[I]32 (RV64P only)
-(define_insn "*riscv_ashl<mode>3"
- [(set (match_operand:VQI 0 "register_operand" "= r, r")
- (ashift:VQI (match_operand:VQI 1 "register_operand" " r, r")
- (match_operand:SI 2 "rimm3u_operand" " u03, r")))]
- "TARGET_ZPN"
- "@
- slli8\t%0, %1, %2
- sll8\t%0, %1, %2"
- [(set_attr "type" "simd, simd")
- (set_attr "mode" "<MODE>, <MODE>")])
-
 (define_insn "*riscv_ashl<mode>3"
  [(set (match_operand:VQI 0 "register_operand" "= r, r")
  (ashift:VQI (match_operand:VQI 1 "register_operand" " r, r")