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Update RISCV-SMBIOS.md
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correct the additional info version
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gilbert225 authored Mar 18, 2019
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Expand Up @@ -86,22 +86,22 @@ RISC-V processor-specific additional information is constructed by RISC-V boot l

| **Offset** | **Additional Info. Version** | **Name**| **Length** | **Value** | **Description**|
|------------|------------------------------|-----------------------------------------------------------------------|------------|-----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 00h | 000Ah (v0.10)| Revision of RISC-V Processor-specific Block Structure | WORD | Varies | Bit 15:8 Major revision Bit 7:0 Minor revision The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure.|
| 02h | 0001h (v1.0) | Structure Length | Byte | 110 | Length of Processor-specific Data |
| 03h | 0001h (v1.0) | Hart ID | DQWORD | Varies | The ID of this RISC-V Hart |
| 13h | 0001h (v1.0) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system <br>0: This is not the boot hart |
| 14h | 0001h (v1.0) | Machine Vendor ID | DQWORD | Varies | The vendor ID of this RISC-V Hart |
| 24h | 0001h (v1.0) | Machine Architecture ID | DQWORD | Varies | Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. |
| 34h | 0001h (v1.0) | Machine Implementation ID | DQWORD | Varies | Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. |
| 44h | 0001h (v1.0) | Instruction set supported | DWORD | Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. |
| 48h | 0001h (v1.0) | Privilege Level Supported | BYTE | Varies | The privilege levels supported by this RISC-V Hart. Bit 0 Machine Mode<br>BIT 1 Reserved<br>BIT 2 Supervisor Mode<br>Bit 3 User Mode<br>BIT 6:4 Reserved<br>BIT 7 Debug Mode |
| 49H | 0001h (v1.0) | Machine Exception Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call.|
| 59H | 0001h (v1.0) | Machine Interrupt Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. |
| 69h | 0001h (v1.0) | The register width (XLEN) | BYTE | ENUM | The width of register supported by this RISC-V Hart |
| 6Ah | 0001h (v1.0) | Machine Mode native base integer ISA width (M-XLEN) | BYTE | ENUM | The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart |
| 6Bh | 0001h (v1.0) | Reserved | BYTE | ENUM | Placeholder for Hypervisor Mode |
| 6Ch | 0001h (v1.0) | Supervisor Mode native base integer ISA width (S-XLEN) | BYTE | ENUM | The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart |
| 6Dh | 00001h (v1.0) | User Mode native base integer ISA width (U-XLEN) | BYTE | ENUM | The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart |
| 00h | 0100h (v1.0)| Revision of RISC-V Processor-specific Block Structure | WORD | 0100h | Bit 15:8 Major revision Bit 7:0 Minor revision The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure.|
| 02h | 0100h (v1.0) | Structure Length | Byte | 110 | Length of Processor-specific Data |
| 03h | 0100h (v1.0) | Hart ID | DQWORD | Varies | The ID of this RISC-V Hart |
| 13h | 0100h (v1.0) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system <br>0: This is not the boot hart |
| 14h | 0100h (v1.0) | Machine Vendor ID | DQWORD | Varies | The vendor ID of this RISC-V Hart |
| 24h | 0100h (v1.0) | Machine Architecture ID | DQWORD | Varies | Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. |
| 34h | 0100h (v1.0) | Machine Implementation ID | DQWORD | Varies | Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. |
| 44h | 0100h (v1.0) | Instruction set supported | DWORD | Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. |
| 48h | 0100h (v1.0) | Privilege Level Supported | BYTE | Varies | The privilege levels supported by this RISC-V Hart. Bit 0 Machine Mode<br>BIT 1 Reserved<br>BIT 2 Supervisor Mode<br>Bit 3 User Mode<br>BIT 6:4 Reserved<br>BIT 7 Debug Mode |
| 49H | 0100h (v1.0) | Machine Exception Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call.|
| 59H | 0100h (v1.0) | Machine Interrupt Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. |
| 69h | 0100h (v1.0) | The register width (XLEN) | BYTE | ENUM | The width of register supported by this RISC-V Hart |
| 6Ah | 0100h (v1.0) | Machine Mode native base integer ISA width (M-XLEN) | BYTE | ENUM | The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart |
| 6Bh | 0100h (v1.0) | Reserved | BYTE | ENUM | Placeholder for Hypervisor Mode |
| 6Ch | 0100h (v1.0) | Supervisor Mode native base integer ISA width (S-XLEN) | BYTE | ENUM | The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart |
| 6Dh | 0100h (v1.0) | User Mode native base integer ISA width (U-XLEN) | BYTE | ENUM | The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart |

### Encoding of RISC-V Native Base Integer ISA Width
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