[#1548][vector crypto] adding register index LMUL alignement checks

[nibrunieAtSi5]

This pull request implement two things:

• (a) fix for issue Should vector crypto instructions constraint vd_num/vs1_num/vs2_num align to lmul? #1548: adding missing LMUL alignment checks for vector crypto instructions. All extensions from the following extensions are affected (that should be all instructions manipulating element groups): Zvkned, Zvknh[a/b], Zvksed, Zvksh, Zvkg.
• (b) implementing precise LMUL alignment checks for the scalar-element-group operand of .vs instruction

(a) the EMUL alignment of vector operand/destination (=EMUL for the vector element group operands and the destination) is specified in the main RVV spec; when a vector register group is not EMUL aligned, the behavior is listed as "reserved" and spike has implemented this check to trigger illegal instruction exception when the condition was not met (e.g.

riscv-isa-sim/riscv/v_ext_macros.h

Line 128 in de5094a

require_align(insn.rd(), P.VU.vflmul); \

)

(b) is not specified clearly in the vector crypto specification (current version https://github.com/riscv/riscv-isa-manual/blob/7023c601443adf21850772e02e3d920bc68b2237/src/vector-crypto.adoc)

The vector crypto specification lists multiple times the intent to allow the vector register group for the scalar-element-group to have EMUL = EGW / VLEN (and to be aligned with this EMUL and not with the global LMUL associated with other vector operands/destination of the instruction).