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Add V extension pseudoinstructions #111

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Add V extension pseudoinstructions #111

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9a975bd
Add V pseudoinstrutions #110
AFOliveira Oct 25, 2024
a8b3580
Complete V pseudoinstrutions
AFOliveira Oct 25, 2024
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26 changes: 26 additions & 0 deletions src/asm-manual.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -1079,6 +1079,32 @@ srli rd, rd, XLEN - 32
|jr rs | jalr x0, rs, 0 | Jump register |
|jalr rs | jalr x1, rs, 0 | Jump and link register |
|ret | jalr x0, x1, 0 | Return from subroutine |
|vfneg.v vd, vs | vfsgnjn.vv vd, vs, vs | Floating-point vector negate |
|vfabs.v vd, vs | vfsgnjx.vv vd, vs, vs | Floating-point vector absolute value |
|vmclr.m vd | vmxor.mm vd, vd, vd | Vector clear mask register |
|vmfge.vv vd, va, vb, vm | vmfle.vv vd, vb, va, vm | Vector Floating-point >=|
|vmfgt.vv vd, va, vb, vm | vmflt.vv vd, vb, va, vm | Vector Floating-point >|
|vmmv.m vd, vs | vmand.mm vd, vs, vs | Vector copy mask register |
|vmnot.m vd, vs | vmnand.mm vd, vs, vs | Vector invert mask bits|
|vmset.m vd | vmxnor.mm vd, vd, vd | Vector set all mask bits|
|vmsge.vi vd, va, i, vm | vmsgt.vi vd, va, i-1, vm | Vector >= Immediate|
|vmsgeu.vi vd, va, i, vm | vmsgtu.vi vd, va, i-1, vm | Vector >= Immediate, unsigned|
|vmsge.vv vd, va, vb, vm | vmsle.vv vd, vb, va, vm | Vector >= Vector|
|vmsgeu.vv vd, va, vb, vm | vmsleu.vv vd, vb, va, vm | Vector >= Vector, unsigned |
|vmsge.vx vd, va, x, vm | vmsle.vx vd, x, va, vm | Vector >= scalar|
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@topperc topperc Nov 21, 2024 •
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This is the not the correct expansion for vmsge.vx

From the spec.

Sequences to synthesize `vmsge{u}.vx` instruction
va >= x,  x > minimum
    addi t0, x, -1; vmsgt{u}.vx vd, va, t0, vm

unmasked va >= x
    pseudoinstruction: vmsge{u}.vx vd, va, x
    expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd

masked va >= x, vd != v0
    pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
    expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0

masked va >= x, vd == v0
    pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
    expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt

masked va >= x, any vd
  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
    expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vt, v0, vt;  vmandn.mm vd, vd,
  v0;  vmor.mm vd, vt, vd
    The vt argument to the pseudoinstruction must name a temporary vector
  register that is
not same as vd and which will be clobbered by the pseudoinstruction

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I'll fix it ASAP, thanks.

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@topperc How can I define this different implementations and follow manual style? Shall I just do a * like in li?

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There are 3 different pseudoinstructions there that should each have their own row

vmsge{u}.vx vd, va, x
vmsge{u}.vx vd, va, x, v0.t // add a note in the last column that vd can't be v0
vmsge{u}.vx vd, va, x, v0.t, vt // you can write the 4 instruction expansion and a note that 2 instructions aren't needed if vd==v0.

|vmsgeu.vx vd, va, x, vm | vmsleu.vx vd, x, va, vm | Vector >= scalar, unsigned|
|vmsgt.vv vd, va, vb, vm | vmslt.vv vd, vb, va, vm | Vector > Vector|
|vmsgtu.vv vd, va, vb, vm | vmsltu.vv vd, vb, va, vm | Vector > Vector, unsigned|
|vmslt.vi vd, va, i, vm | vmsle.vi vd, va, i-1, vm | Vector < immediate|
|vmsltu.vi vd, va, i, vm | vmsleu.vi vd, va, i-1, vm | Vector < immediate, unsigned |
|vneg.v vd,vs | vrsub.vx vd,vs,x0 | Vector negate |
|vnot.v vd,vs,vm | vxor.vi vd, vs, -1, vm | Vector not |
|vwcvt.x.x.v vd,vs,vm | vwadd.vx vd,vs,x0,vm | Vector widen convert, integer-integer|
|vwcvtu.x.x.v vd,vs,vm | vwaddu.vx vd,vs,x0,vm | Vector widen convert, integer-integer, unsigned|





|call offset
|auipc x1, offset[31:12] +
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