Add V extension pseudoinstructions #111
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Signed-off-by: Afonso Oliveira <[email protected]>
Signed-off-by: Afonso Oliveira <[email protected]>
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@cmuellner I added the ones you mentioned, but I couldn't really find many more. |
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@cmuellner just a quick ping, is there anything else I should enhance in the PR? |
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👀 :) |
| |vmsgeu.vi vd, va, i, vm | vmsgtu.vi vd, va, i-1, vm | Vector >= Immediate, unsigned| | ||
| |vmsge.vv vd, va, vb, vm | vmsle.vv vd, vb, va, vm | Vector >= Vector| | ||
| |vmsgeu.vv vd, va, vb, vm | vmsleu.vv vd, vb, va, vm | Vector >= Vector, unsigned | | ||
| |vmsge.vx vd, va, x, vm | vmsle.vx vd, x, va, vm | Vector >= scalar| |
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This is the not the correct expansion for vmsge.vx
From the spec.
Sequences to synthesize `vmsge{u}.vx` instruction
va >= x, x > minimum
addi t0, x, -1; vmsgt{u}.vx vd, va, t0, vm
unmasked va >= x
pseudoinstruction: vmsge{u}.vx vd, va, x
expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
masked va >= x, vd != v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
masked va >= x, vd == v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
masked va >= x, any vd
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd, vd,
v0; vmor.mm vd, vt, vd
The vt argument to the pseudoinstruction must name a temporary vector
register that is
not same as vd and which will be clobbered by the pseudoinstruction
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@topperc How can I define this different implementations and follow manual style? Shall I just do a * like in li?
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There are 3 different pseudoinstructions there that should each have their own row
vmsge{u}.vx vd, va, x
vmsge{u}.vx vd, va, x, v0.t // add a note in the last column that vd can't be v0
vmsge{u}.vx vd, va, x, v0.t, vt // you can write the 4 instruction expansion and a note that 2 instructions aren't needed if vd==v0.
Closes #110 .
Preview: riscv-asm.pdf