convert wavedrom signal to adoc table

initial proof of concept; relates to #34

Signed-off-by: Kevin Broch <[email protected]>

projects/csr-format/Makefile

@@ -0,0 +1,10 @@
+
+REG := \
+	zabha-ext-reg
+
+DST = $(addsuffix -table.adoc, $(REG))
+
+%-table.adoc: %-wavedrom.json5 wavedrom-bitfield-to-adoc-table.j2
+	jinja2 --strict -f json5 -o $@ wavedrom-bitfield-to-adoc-table.j2 $<
+
+all: $(DST)

projects/csr-format/wavedrom-bitfield-to-adoc-table.j2

@@ -0,0 +1,12 @@
+[cols="2,1,3,16"]
+|===
+|Bit Range | Bits | Name |Attributes
+{%- set br = namespace(lsb=0) -%}
+{% for fld in reg %}
+|{{ fld.bits + br.lsb - 1 }}:{{ br.lsb }}
+|{{ fld.bits }}
+|{% if fld.attr is defined %}{{ fld.name }}{% endif %}
+|{% if fld.attr is defined %}{{ fld.attr }}{% endif %}
+{%- set br.lsb = br.lsb + fld.bits -%}
+{% endfor %}
+|===

projects/csr-format/wavedrom-input.adoc

@@ -0,0 +1,34 @@
+# Wavedrom input
+
+## Overview
+
+Demonstrate wavedrom input converted to other outputs (ex: table)
+
+## Example
+
+.Zabha register
+[wavedrom, zabha-ext-wavedrom-reg, svg]
+....
+include::zabha-ext-reg-wavedrom.json5[]
+....
+
+.Zabha register
+include::zabha-ext-reg-table.adoc[]
+
+
+## Implementation details
+
+* install prerequisites:
+** `pip install jinja2-cli[json5]`
+* pull out existing wavedrom definitions from adoc file into a separate json5 file
+* replace that with include
+* write a jinja2 template to convert wavedrom json5 into asciidoc
+[source, jinja]
+----
+include::wavedrom-bitfield-to-adoc-table.j2[]
+----
+* write Makefile to build the adoc table:
+[source, make]
+----
+include::Makefile[]
+----

projects/csr-format/zabha-ext-reg-table.adoc

@@ -0,0 +1,36 @@
+[cols="2,1,3,16"]
+|===
+|Bit Range | Bits | Name |Attributes
+|6:0
+|7
+|opcode
+|['AMO', 'AMO', 'AMO', 'AMO', 'AMO', 'AMO', 'AMO', 'AMO']
+|11:7
+|5
+|rd
+|['dest', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest']
+|14:12
+|3
+|funct3
+|['width=0/1', 'width=0/1', 'width=0/1', 'width=0/1', 'width=0/1', 'width=0/1', 'width=0/1', 'width=0/1']
+|19:15
+|5
+|rs1
+|['addr', 'addr', 'addr', 'addr', 'addr', 'addr', 'addr', 'addr']
+|24:20
+|5
+|rs2
+|['src', 'src', 'src', 'src', 'src', 'src', 'src', 'src']
+|25:25
+|1
+|
+|
+|26:26
+|1
+|aq
+|['ordering', 'ordering', 'ordering', 'ordering', 'ordering', 'ordering', 'ordering', 'ordering']
+|31:27
+|5
+|funct5
+|['AMOSWAP.B/H', 'AMOADD.B/H', 'AMOAND.B/H', 'AMOOR.B/H', 'AMOXOR.B/H', 'AMOMAX[U].B/H', 'AMOMIN[U].B/H', 'AMOCAS.B/H']
+|===

projects/csr-format/zabha-ext-reg-wavedrom.json5

@@ -0,0 +1,68 @@
+{
+  reg: [
+    {
+      bits: 7,
+      name: "opcode",
+      attr: ["AMO", "AMO", "AMO", "AMO", "AMO", "AMO", "AMO", "AMO"],
+    },
+    {
+      bits: 5,
+      name: "rd",
+      attr: ["dest", "dest", "dest", "dest", "dest", "dest", "dest", "dest"],
+    },
+    {
+      bits: 3,
+      name: "funct3",
+      attr: [
+        "width=0/1",
+        "width=0/1",
+        "width=0/1",
+        "width=0/1",
+        "width=0/1",
+        "width=0/1",
+        "width=0/1",
+        "width=0/1",
+      ],
+    },
+    {
+      bits: 5,
+      name: "rs1",
+      attr: ["addr", "addr", "addr", "addr", "addr", "addr", "addr", "addr"],
+    },
+    {
+      bits: 5,
+      name: "rs2",
+      attr: ["src", "src", "src", "src", "src", "src", "src", "src"],
+    },
+    { bits: 1 },
+    {
+      bits: 1,
+      name: "aq",
+      attr: [
+        "ordering",
+        "ordering",
+        "ordering",
+        "ordering",
+        "ordering",
+        "ordering",
+        "ordering",
+        "ordering",
+      ],
+    },
+    {
+      bits: 5,
+      name: "funct5",
+      attr: [
+        "AMOSWAP.B/H",
+        "AMOADD.B/H",
+        "AMOAND.B/H",
+        "AMOOR.B/H",
+        "AMOXOR.B/H",
+        "AMOMAX[U].B/H",
+        "AMOMIN[U].B/H",
+        "AMOCAS.B/H",
+      ],
+    },
+  ],
+  config: { lanes: 1, hspace: 1024 },
+}