Implement risc zero accelerator on p256 #4
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Description
Building on risc0/risc0#466 and referencing #1, this PR enables the use of the RISC Zero 256-bit modular multiplication accelerator within guest code for p256 arithmetic, including ECDSA.
A key application, ECDSA verification is accelerated significantly from a little over 13M cycles without acceleration support to about 8M cycles.
Based on [email protected]
Testing