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revolver-ocelot-saa committed Aug 26, 2019
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88 changes: 88 additions & 0 deletions .gitignore
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# Compiled class file
*.class

# Log file
*.log

# BlueJ files
*.ctxt

# Mobile Tools for Java (J2ME)
.mtj.tmp/

# Package Files #
*.jar
*.war
*.nar
*.ear
*.zip
*.tar.gz
*.rar

# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
hs_err_pid*

# Eclipse dirs
.metadata
bin/
tmp/
*.tmp
*.bak
*.swp
*~.nib
local.properties
.settings/
.loadpath
.recommenders

# External tool builders
.externalToolBuilders/

# Locally stored "Eclipse launch configurations"
*.launch

# PyDev specific (Python IDE for Eclipse)
*.pydevproject

# CDT-specific (C/C++ Development Tooling)
.cproject

# CDT- autotools
.autotools

# Java annotation processor (APT)
.factorypath

# PDT-specific (PHP Development Tools)
.buildpath

# sbteclipse plugin
.target

# Tern plugin
.tern-project

# TeXlipse plugin
.texlipse

# STS (Spring Tool Suite)
.springBeans

# Code Recommenders
.recommenders/

# Annotation Processing
.apt_generated/

# Scala IDE specific (Scala & Java development for Eclipse)
.cache-main
.scala_dependencies
.worksheet

# Extra
.antProperties.xml
.classpath
.project
.gradle
build
build.gradle
19 changes: 19 additions & 0 deletions LICENSE
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Copyright (c) 2019 revolver-ocelot-saa

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
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14 changes: 14 additions & 0 deletions README.md
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## GhidraX64Dbg
Extension containing a Ghidra script to export annotations from Ghidra to an X32/X64 database.

## Easy Installation
1. From the releases tab download the zip file
2. Open Ghidra and select File -> Install Extensions
3. Install the extension
4. Open a binary in Ghidra
5. Open Window -> Script Manager
6. Select the X64DbgExport script and execute it

## License
GSON is a dependency and follows the Apache license.
Everything I wrote in this repository follows the MIT license.
15 changes: 15 additions & 0 deletions data/README.txt
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The "data" directory is intended to hold data files that will be used by this module and will
not end up in the .jar file, but will be present in the zip or tar file. Typically, data
files are placed here rather than in the resources directory if the user may need to edit them.

An optional data/languages directory can exist for the purpose of containing various Sleigh language
specification files and importer opinion files.

The data/build.xml is used for building the contents of the data/languages directory.

The skel language definition has been commented-out within the skel.ldefs file so that the
skeleton language does not show-up within Ghidra.

See the Sleigh language documentation (docs/languages/sleigh.htm or sleigh.pdf) for details
on Sleigh language specification syntax.

50 changes: 50 additions & 0 deletions data/build.xml
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<?xml version="1.0" encoding="UTF-8"?>

<!--
+ Compile sleigh languages within this module.
+ Sleigh compiler options are read from the sleighArgs.txt file.
+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
-->

<project name="privateBuildDeveloper" default="sleighCompile">

<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>

<!--Import optional ant properties. GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
<import file="../.antProperties.xml" optional="false" />

<target name="sleighCompile">

<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
<property name="framework.path" value="${ghidra.install.dir}/Ghidra/Framework"/>

<path id="sleigh.class.path">
<fileset dir="${framework.path}/SoftwareModeling/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Generic/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Utility/lib">
<include name="*.jar"/>
</fileset>
</path>

<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>

<fail unless="sleigh.compile.exists" />

<java classname="${sleigh.compile.class}"
classpathref="sleigh.class.path"
fork="true"
failonerror="true">
<jvmarg value="-Xmx2048M"/>
<arg value="-i"/>
<arg value="sleighArgs.txt"/>
<arg value="-a"/>
<arg value="./languages"/>
</java>

</target>

</project>
129 changes: 129 additions & 0 deletions data/languages/skel.cspec
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<?xml version="1.0" encoding="UTF-8"?>

<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/compiler_spec.rxg -->

<compiler_spec>
<data_organization>
<pointer_size value="2" />
</data_organization>
<global>
<range space="ram"/>
<range space="io"/>
</global>
<stackpointer register="SP" space="ram"/>
<segmentop space="ram" userop="segment" baseinsize="2" innerinsize="2" farpointer="yes">
<baseop code="INT_ZEXT"/>
<baseop code="INT_LEFT" value="12"/>
<innerop code="INT_ZEXT"/>
<constresolve>
<register name="rBBR"/>
</constresolve>
</segmentop>
<default_proto>
<prototype name="__asmA" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DE"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
<register name="rBBR"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="__asmAF" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DE"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AF"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="rBBR"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
</unaffected>
</prototype>
<prototype name="__stdcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="AF"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="rBBR"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
</unaffected>
</prototype>
</compiler_spec>
20 changes: 20 additions & 0 deletions data/languages/skel.ldefs
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<?xml version="1.0" encoding="UTF-8"?>

<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/language_definitions.rxg -->

<language_definitions>
<!-- Uncomment the following to make the language available in Ghidra -->
<!--
<language processor="Skel"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="skel.sla"
processorspec="skel.pspec"
id="skel:LE:16:default">
<description>Skeleton Language Module</description>
<compiler name="default" spec="skel.cspec" id="default"/>
</language>
-->
</language_definitions>
12 changes: 12 additions & 0 deletions data/languages/skel.opinion
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<opinions>
<!-- Example of importer opinions - commented-out to prevent use by Ghidra -->
<!-- The primary and secondary constraint values must be specifide as a decimal string -->
<!--
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="40" secondary="123" processor="Skel" size="16" variant="default" />
</constraint>
<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="default">
<constraint primary="61" processor="Skel" size="16" variant="default" />
</constraint>
-->
</opinions>
23 changes: 23 additions & 0 deletions data/languages/skel.pspec
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<?xml version="1.0" encoding="UTF-8"?>

<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg -->

<processor_spec>
<programcounter register="PC"/>
<register_data>
<register name="AF_" group="Alt"/>
<register name="BC_" group="Alt"/>
<register name="DE_" group="Alt"/>
<register name="HL_" group="Alt"/>
</register_data>
<default_symbols>
<symbol name="RST0" address="ram:0000" entry="true"/>
<symbol name="RST1" address="ram:0008" entry="false"/>
<symbol name="RST2" address="ram:0010" entry="false"/>
<symbol name="RST3" address="ram:0018" entry="false"/>
<symbol name="RST4" address="ram:0020" entry="false"/>
<symbol name="RST5" address="ram:0028" entry="false"/>
<symbol name="RST6" address="ram:0030" entry="false"/>
<symbol name="RST7" address="ram:0038" entry="false"/>
</default_symbols>
</processor_spec>
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