Skip to content

Commit

Permalink
Merge branch 'main' into target-variadic
Browse files Browse the repository at this point in the history
  • Loading branch information
raynelfss authored Aug 14, 2024
2 parents 95f265f + 592c5f4 commit d0e30cf
Show file tree
Hide file tree
Showing 19 changed files with 697 additions and 209 deletions.
4 changes: 2 additions & 2 deletions Cargo.lock

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ license = "Apache-2.0"
# Each crate can add on specific features freely as it inherits.
[workspace.dependencies]
bytemuck = "1.16"
indexmap.version = "2.3.0"
indexmap.version = "2.4.0"
hashbrown.version = "0.14.0"
num-bigint = "0.4"
num-complex = "0.4"
Expand Down
6 changes: 3 additions & 3 deletions qiskit/circuit/add_control.py
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,7 @@ def control(
gate.definition.data[0].operation.params[0],
q_control,
q_target[bit_indices[qargs[0]]],
use_basis_gates=True,
use_basis_gates=False,
)
elif gate.name == "ry":
controlled_circ.mcry(
Expand All @@ -146,14 +146,14 @@ def control(
q_target[bit_indices[qargs[0]]],
q_ancillae,
mode="noancilla",
use_basis_gates=True,
use_basis_gates=False,
)
elif gate.name == "rz":
controlled_circ.mcrz(
gate.definition.data[0].operation.params[0],
q_control,
q_target[bit_indices[qargs[0]]],
use_basis_gates=True,
use_basis_gates=False,
)
continue
elif gate.name == "p":
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -200,7 +200,7 @@ def _mcsu2_real_diagonal(
circuit.h(target)

if use_basis_gates:
circuit = transpile(circuit, basis_gates=["p", "u", "cx"])
circuit = transpile(circuit, basis_gates=["p", "u", "cx"], qubits_initially_zero=False)

return circuit

Expand Down
3 changes: 2 additions & 1 deletion qiskit/circuit/library/standard_gates/p.py
Original file line number Diff line number Diff line change
Expand Up @@ -377,7 +377,8 @@ def _define(self):
q_target = self.num_ctrl_qubits
new_target = q_target
for k in range(self.num_ctrl_qubits):
qc.mcrz(lam / (2**k), q_controls, new_target, use_basis_gates=True)
# Note: it's better *not* to run transpile recursively
qc.mcrz(lam / (2**k), q_controls, new_target, use_basis_gates=False)
new_target = q_controls.pop()
qc.p(lam / (2**self.num_ctrl_qubits), new_target)
else: # in this case type(lam) is ParameterValueType
Expand Down
3 changes: 3 additions & 0 deletions qiskit/compiler/transpiler.py
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@ def transpile( # pylint: disable=too-many-return-statements
optimization_method: Optional[str] = None,
ignore_backend_supplied_default_methods: bool = False,
num_processes: Optional[int] = None,
qubits_initially_zero: bool = True,
) -> _CircuitT:
"""Transpile one or more circuits, according to some desired transpilation targets.
Expand Down Expand Up @@ -284,6 +285,7 @@ def callback_func(**kwargs):
``num_processes`` in the user configuration file, and the ``QISKIT_NUM_PROCS``
environment variable. If set to ``None`` the system default or local user configuration
will be used.
qubits_initially_zero: Indicates whether the input circuit is zero-initialized.
Returns:
The transpiled circuit(s).
Expand Down Expand Up @@ -386,6 +388,7 @@ def callback_func(**kwargs):
init_method=init_method,
optimization_method=optimization_method,
dt=dt,
qubits_initially_zero=qubits_initially_zero,
)

out_circuits = pm.run(circuits, callback=callback, num_processes=num_processes)
Expand Down
4 changes: 3 additions & 1 deletion qiskit/synthesis/unitary/qsd.py
Original file line number Diff line number Diff line change
Expand Up @@ -255,7 +255,9 @@ def _apply_a2(circ):
from qiskit.circuit.library.generalized_gates.unitary import UnitaryGate

decomposer = two_qubit_decompose_up_to_diagonal
ccirc = transpile(circ, basis_gates=["u", "cx", "qsd2q"], optimization_level=0)
ccirc = transpile(
circ, basis_gates=["u", "cx", "qsd2q"], optimization_level=0, qubits_initially_zero=False
)
ind2q = []
# collect 2q instrs
for i, instruction in enumerate(ccirc.data):
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@
from qiskit.circuit.delay import Delay
from qiskit.circuit.library.standard_gates import IGate, UGate, U3Gate
from qiskit.circuit.reset import Reset
from qiskit.dagcircuit import DAGCircuit, DAGNode, DAGInNode, DAGOpNode
from qiskit.dagcircuit import DAGCircuit, DAGNode, DAGInNode, DAGOpNode, DAGOutNode
from qiskit.quantum_info.operators.predicates import matrix_equal
from qiskit.synthesis.one_qubit import OneQubitEulerDecomposer
from qiskit.transpiler.exceptions import TranspilerError
Expand Down Expand Up @@ -331,8 +331,7 @@ def _pad(
if time_interval % self._alignment != 0:
raise TranspilerError(
f"Time interval {time_interval} is not divisible by alignment {self._alignment} "
f"between DAGNode {prev_node.name} on qargs {prev_node.qargs} and {next_node.name} "
f"on qargs {next_node.qargs}."
f"between {_format_node(prev_node)} and {_format_node(next_node)}."
)

if not self.__is_dd_qubit(dag.qubits.index(qubit)):
Expand Down Expand Up @@ -430,3 +429,10 @@ def _resolve_params(gate: Gate) -> tuple:
else:
params.append(p)
return tuple(params)


def _format_node(node: DAGNode) -> str:
"""Util to format the DAGNode, DAGInNode, and DAGOutNode."""
if isinstance(node, (DAGInNode, DAGOutNode)):
return f"{node.__class__.__name__} on qarg {node.wire}"
return f"DAGNode {node.name} on qargs {node.qargs}"
Loading

0 comments on commit d0e30cf

Please sign in to comment.