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Add hazard3 instructions to asm_helper. Split hazard3.h to support this.
You can still include hazard3.h to get everything. This just allows you to pull in less.
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29 changes: 29 additions & 0 deletions
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src/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h
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| /* | ||
| * Copyright (c) 2024 Raspberry Pi Ltd. | ||
| * | ||
| * SPDX-License-Identifier: BSD-3-Clause | ||
| */ | ||
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| #ifndef _HARDWARE_HAZARD3_FEATURES_ | ||
| #define _HARDWARE_HAZARD3_FEATURES_ | ||
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| #include "pico.h" | ||
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| /** \file hardware/hazard3/features.h | ||
| * \addtogroup hardware_hazard3 | ||
| * | ||
| * \brief Sets macros for supported Hazard3 custom extensions (features) based on PICO_PLATFORM macros | ||
| * | ||
| */ | ||
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| // Feature detection macros for Hazard3 custom extensions | ||
| #if PICO_RP2350 | ||
| // Version 1.0 of these four extensions | ||
| // (encoded as major * 100 + minor) | ||
| #define __hazard3_extension_xh3power 100 | ||
| #define __hazard3_extension_xh3bextm 100 | ||
| #define __hazard3_extension_xh3irq 100 | ||
| #define __hazard3_extension_xh3pmpm 100 | ||
| #endif | ||
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| #endif |
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src/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h
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| /* | ||
| * Copyright (c) 2024 Raspberry Pi Ltd. | ||
| * | ||
| * SPDX-License-Identifier: BSD-3-Clause | ||
| */ | ||
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| #ifndef _HARDWARE_HAZARD3_INSTRUCTIONS_ | ||
| #define _HARDWARE_HAZARD3_INSTRUCTIONS_ | ||
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| #include "pico.h" | ||
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| // Get list of supported extensions based on platform: | ||
| #include "hardware/hazard3/features.h" | ||
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| /** \file hardware/hazard3/instructions.h | ||
| * \addtogroup hardware_hazard3 | ||
| * | ||
| * \brief Intrinsics and asm macros for Hazard3 custom instructions | ||
| * | ||
| * The implementation of these intrinsics depends on the feature macros | ||
| * defined in hardware/hazard3/features.h. When the relevant feature is not | ||
| * present, the intrinsics fall back on an RV32I equivalent if possible. | ||
| * | ||
| */ | ||
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| #ifdef __ASSEMBLER__ | ||
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| // Assembly language instruction macros for Hazard3 custom instructions | ||
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| // h3.bextm: Extract up to 8 consecutive bits from register rs1, with the | ||
| // first bit indexed by rs2, and bit count configured by an immediate value. | ||
| // R-format instruction. Pseudocode: | ||
| // | ||
| // rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits) | ||
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| .macro h3.bextm rd rs1 rs2 nbits | ||
| .if (\nbits < 1) || (\nbits > 8) | ||
| .err | ||
| .endif | ||
| #ifdef __hazard3_extension_xh3bextm | ||
| .insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2 | ||
| #else | ||
| srl \rd, \rs1, \rs2 | ||
| andi \rd, \rd, ((1 << \nbits) - 1) | ||
| #endif | ||
| .endm | ||
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| // h3.bextmi: Extract up to 8 consecutive bits from register rs1, with the | ||
| // first bit index and the number of bits both configured by immediate | ||
| // values. I-format instruction. Pseudocode: | ||
| // | ||
| // rd = (rs1 >> shamt) & ~(-1 << nbits) | ||
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| .macro h3.bextmi rd rs1 shamt nbits | ||
| .if (\nbits < 1) || (\nbits > 8) | ||
| .err | ||
| .endif | ||
| .if (\shamt < 0) || (\shamt > 31) | ||
| .err | ||
| .endif | ||
| #ifdef __hazard3_extension_xh3bextm | ||
| .insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6) | ||
| #else | ||
| srli \rd, \rs1, \shamt | ||
| andi \rd, \rd, ((1 << \nbits) - 1) | ||
| #endif | ||
| .endm | ||
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| // h3.block: enter an idle state until another processor in the same | ||
| // multiprocessor complex executes an h3.unblock instruction, or the | ||
| // processor is interrupted. Fall through immediately if an h3.unblock has | ||
| // been received since the last execution of an h3.block on this processor. | ||
| // On RP2350, processors also have their own h3.unblock signals reflected | ||
| // back to them. | ||
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| .macro h3.block | ||
| #ifdef __hazard3_extension_xh3power | ||
| slt x0, x0, x0 | ||
| #else | ||
| nop | ||
| #endif | ||
| .endm | ||
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| // h3.unblock: signal other processors in the same multiprocessor complex to | ||
| // exit the idle state entered by an h3.block instruction. On RP2350, this | ||
| // signal is also reflected back to the processor that executed the | ||
| // h3.unblock, which will cause that processor's next h3.block to fall | ||
| // through immediately. | ||
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| .macro h3.unblock | ||
| #ifdef __hazard3_extension_xh3power | ||
| slt x0, x0, x1 | ||
| #else | ||
| nop | ||
| #endif | ||
| .endm | ||
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| #else // !__ASSEMBLER__ | ||
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| // C language instruction macros for Hazard3 custom instructions | ||
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| #ifdef __cplusplus | ||
| extern "C" { | ||
| #endif | ||
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| // nbits must be a constant expression | ||
| #ifdef __hazard3_extension_xh3bextm | ||
| #define __hazard3_bextm(nbits, rs1, rs2) ({\ | ||
| uint32_t __h3_bextm_rd; \ | ||
| asm (".insn r 0x0b, 0, %3, %0, %1, %2"\ | ||
| : "=r" (__h3_bextm_rd) \ | ||
| : "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\ | ||
| ); \ | ||
| __h3_bextm_rd; \ | ||
| }) | ||
| #else | ||
| #define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((rs2) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) | ||
| #endif | ||
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| // nbits and shamt must be constant expressions | ||
| #ifdef __hazard3_extension_xh3bextm | ||
| #define __hazard3_bextmi(nbits, rs1, shamt) ({\ | ||
| uint32_t __h3_bextmi_rd; \ | ||
| asm (".insn i 0x0b, 0x4, %0, %1, %2"\ | ||
| : "=r" (__h3_bextmi_rd) \ | ||
| : "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \ | ||
| ); \ | ||
| __h3_bextmi_rd; \ | ||
| }) | ||
| #else | ||
| #define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((shamt) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) | ||
| #endif | ||
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| #ifdef __hazard3_extension_xh3power | ||
| #define __hazard3_block() asm volatile ("slt x0, x0, x0" : : : "memory") | ||
| #else | ||
| #define __hazard3_block() do {} while (0) | ||
| #endif | ||
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| #ifdef __hazard3_extension_xh3power | ||
| #define __hazard3_unblock() asm volatile ("slt x0, x0, x1" : : : "memory") | ||
| #else | ||
| #define __hazard3_unblock() do {} while (0) | ||
| #endif | ||
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| #ifdef __cplusplus | ||
| } | ||
| #endif | ||
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| #endif // !__ASSEMBLER__ | ||
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| #endif |