drivers: media: pci: Update Hailo accelerator device driver to v4.19

drivers/media/pci/hailo/Makefile

@@ -8,9 +8,9 @@ obj-$(CONFIG_MEDIA_PCI_HAILO) := hailo_pci.o
 
 hailo_pci-objs += src/pcie.o
 hailo_pci-objs += src/fops.o
-hailo_pci-objs += src/utils.o
 hailo_pci-objs += src/sysfs.o
-hailo_pci-objs += src/pci_soc_ioctl.o
+hailo_pci-objs += src/nnc.o
+hailo_pci-objs += src/soc.o
 
 hailo_pci-objs += $(COMMON_SRC_DIRECTORY)/fw_validation.o
 hailo_pci-objs += $(COMMON_SRC_DIRECTORY)/fw_operation.o

drivers/media/pci/hailo/common/fw_operation.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: MIT
 /**
- * Copyright (c) 2022 Hailo Technologies Ltd. All rights reserved.
-**/
+ * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved.
+ **/
 
 #include "fw_operation.h"
 
@@ -15,7 +15,10 @@
     u32 chip_offset;
 } FW_DEBUG_BUFFER_HEADER_t;
 
-#define DEBUG_BUFFER_DATA_SIZE (DEBUG_BUFFER_TOTAL_SIZE - sizeof(FW_DEBUG_BUFFER_HEADER_t))
+#define DEBUG_BUFFER_DATA_SIZE              (DEBUG_BUFFER_TOTAL_SIZE - sizeof(FW_DEBUG_BUFFER_HEADER_t))
+#define PCIE_D2H_NOTIFICATION_SRAM_OFFSET   (0x640 + 0x640)
+#define PCIE_APP_CPU_DEBUG_OFFSET           (8*1024)
+#define PCIE_CORE_CPU_DEBUG_OFFSET          (PCIE_APP_CPU_DEBUG_OFFSET + DEBUG_BUFFER_TOTAL_SIZE)
 
 int hailo_read_firmware_notification(struct hailo_resource *resource, struct hailo_d2h_notification *notification)
 {
@@ -35,6 +38,21 @@
     return 0;
 }
 
+int hailo_pcie_read_firmware_notification(struct hailo_resource *resource,
+    struct hailo_d2h_notification *notification)
+{
+    struct hailo_resource notification_resource;
+
+    if (PCIE_D2H_NOTIFICATION_SRAM_OFFSET > resource->size) {
+        return -EINVAL;
+    }
+
+    notification_resource.address = resource->address + PCIE_D2H_NOTIFICATION_SRAM_OFFSET,
+    notification_resource.size = sizeof(struct hailo_d2h_notification);
+
+    return hailo_read_firmware_notification(&notification_resource, notification);
+}
+
 static inline size_t calculate_log_ready_to_read(FW_DEBUG_BUFFER_HEADER_t *header)
 {
     size_t ready_to_read = 0;
@@ -99,5 +117,31 @@
         (u32)(read_offset - sizeof(debug_buffer_header)));
 
     params->read_bytes = ready_to_read;
+    return 0;
+}
+
+long hailo_pcie_read_firmware_log(struct hailo_resource *resource, struct hailo_read_log_params *params)
+{
+    long err = 0;
+    struct hailo_resource log_resource = {resource->address, DEBUG_BUFFER_TOTAL_SIZE};
+
+    if (HAILO_CPU_ID_CPU0 == params->cpu_id) {
+        log_resource.address += PCIE_APP_CPU_DEBUG_OFFSET;
+    } else if (HAILO_CPU_ID_CPU1 == params->cpu_id) {
+        log_resource.address += PCIE_CORE_CPU_DEBUG_OFFSET;
+    } else {
+        return -EINVAL;
+    }
+
+    if (0 == params->buffer_size) {
+        params->read_bytes = 0;
+        return 0;
+    }
+
+    err = hailo_read_firmware_log(&log_resource, params);
+    if (0 != err) {
+        return err;
+    }
+
     return 0;
 }

drivers/media/pci/hailo/common/fw_operation.h

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: MIT
 /**
- * Copyright (c) 2022 Hailo Technologies Ltd. All rights reserved.
-**/
+ * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved.
+ **/
 
 #ifndef _HAILO_COMMON_FIRMWARE_OPERATION_H_
 #define _HAILO_COMMON_FIRMWARE_OPERATION_H_
@@ -16,8 +16,12 @@ extern "C" {
 
 int hailo_read_firmware_notification(struct hailo_resource *resource, struct hailo_d2h_notification *notification);
 
+int hailo_pcie_read_firmware_notification(struct hailo_resource *resource, struct hailo_d2h_notification *notification);
+
 long hailo_read_firmware_log(struct hailo_resource *fw_logger_resource, struct hailo_read_log_params *params);
 
+long hailo_pcie_read_firmware_log(struct hailo_resource *resource, struct hailo_read_log_params *params);
+
 #ifdef __cplusplus
 }
 #endif

drivers/media/pci/hailo/common/fw_validation.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MIT
 /**
- * Copyright (c) 2019-2022 Hailo Technologies Ltd. All rights reserved.
+ * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved.
  **/
 
 #include "fw_validation.h"
@@ -85,15 +85,15 @@ int FW_VALIDATION__validate_fw_header(uintptr_t firmware_base_address,
 }
 
 int FW_VALIDATION__validate_cert_header(uintptr_t firmware_base_address,
-    size_t firmware_size, u32 *outer_consumed_firmware_offset, secure_boot_certificate_t **out_firmware_cert)
+    size_t firmware_size, u32 *outer_consumed_firmware_offset, secure_boot_certificate_header_t **out_firmware_cert)
 {
 
-    secure_boot_certificate_t *firmware_cert = NULL;
+    secure_boot_certificate_header_t *firmware_cert = NULL;
     int err = -EINVAL;
     u32 consumed_firmware_offset = *outer_consumed_firmware_offset;
 
-    firmware_cert = (secure_boot_certificate_t *) (firmware_base_address + consumed_firmware_offset);
-    CONSUME_FIRMWARE(sizeof(secure_boot_certificate_t), -EINVAL);
+    firmware_cert = (secure_boot_certificate_header_t *) (firmware_base_address + consumed_firmware_offset);
+    CONSUME_FIRMWARE(sizeof(secure_boot_certificate_header_t), -EINVAL);
 
     if ((MAXIMUM_FIRMWARE_CERT_KEY_SIZE < firmware_cert->key_size) ||
         (MAXIMUM_FIRMWARE_CERT_CONTENT_SIZE < firmware_cert->content_size)) {

drivers/media/pci/hailo/common/fw_validation.h

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MIT
 /**
- * Copyright (c) 2019-2022 Hailo Technologies Ltd. All rights reserved.
+ * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved.
  **/
 
 #ifndef PCIE_COMMON_FIRMWARE_HEADER_UTILS_H_
@@ -44,8 +44,7 @@ typedef struct {
 typedef struct {
     u32 key_size;
     u32 content_size;
-    u8 certificates_data[0];
-} secure_boot_certificate_t;
+} secure_boot_certificate_header_t;
 
 #ifdef _MSC_VER
 #pragma warning(pop)
@@ -60,6 +59,6 @@ int FW_VALIDATION__validate_fw_header(uintptr_t firmware_base_address,
     firmware_header_t **out_firmware_header, enum hailo_board_type board_type);
 
 int FW_VALIDATION__validate_cert_header(uintptr_t firmware_base_address,
-    size_t firmware_size, u32 *outer_consumed_firmware_offset, secure_boot_certificate_t **out_firmware_cert);
+    size_t firmware_size, u32 *outer_consumed_firmware_offset, secure_boot_certificate_header_t **out_firmware_cert);
 
 #endif

drivers/media/pci/hailo/common/hailo_ioctl_common.h

@@ -1,13 +1,13 @@
 // SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) AND MIT
 /**
- * Copyright (c) 2019-2022 Hailo Technologies Ltd. All rights reserved.
+ * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved.
  **/
 
 #ifndef _HAILO_IOCTL_COMMON_H_
 #define _HAILO_IOCTL_COMMON_H_
 
 #define HAILO_DRV_VER_MAJOR 4
-#define HAILO_DRV_VER_MINOR 18
+#define HAILO_DRV_VER_MINOR 19
 #define HAILO_DRV_VER_REVISION 0
 
 #define _STRINGIFY_EXPANDED( x ) #x
@@ -17,10 +17,11 @@
 
 // This value is not easily changeable.
 // For example: the channel interrupts ioctls assume we have up to 32 channels
-#define MAX_VDMA_CHANNELS_PER_ENGINE    (32)
-#define MAX_VDMA_ENGINES                (3)
-#define SIZE_OF_VDMA_DESCRIPTOR         (16)
-#define VDMA_DEST_CHANNELS_START        (16)
+#define MAX_VDMA_CHANNELS_PER_ENGINE            (32)
+#define VDMA_CHANNELS_PER_ENGINE_PER_DIRECTION  (16)
+#define MAX_VDMA_ENGINES                        (3)
+#define SIZE_OF_VDMA_DESCRIPTOR                 (16)
+#define VDMA_DEST_CHANNELS_START                (16)
 
 #define HAILO_VDMA_MAX_ONGOING_TRANSFERS (128)
 #define HAILO_VDMA_MAX_ONGOING_TRANSFERS_MASK (HAILO_VDMA_MAX_ONGOING_TRANSFERS - 1)
@@ -37,8 +38,8 @@
 #define FW_ACCESS_APP_CPU_CONTROL_MASK      (1 << FW_ACCESS_CONTROL_INTERRUPT_SHIFT)
 #define FW_ACCESS_DRIVER_SHUTDOWN_SHIFT     (2)
 #define FW_ACCESS_DRIVER_SHUTDOWN_MASK      (1 << FW_ACCESS_DRIVER_SHUTDOWN_SHIFT)
-#define FW_ACCESS_SOC_CONNECT_SHIFT         (3)
-#define FW_ACCESS_SOC_CONNECT_MASK          (1 << FW_ACCESS_SOC_CONNECT_SHIFT)
+#define FW_ACCESS_SOC_CONTROL_SHIFT         (3)
+#define FW_ACCESS_SOC_CONTROL_MASK          (1 << FW_ACCESS_SOC_CONTROL_SHIFT)
 
 #define INVALID_VDMA_CHANNEL                (0xff)
 
@@ -245,6 +246,12 @@ struct hailo_desc_list_release_params {
     uintptr_t desc_handle;      // in
 };
 
+struct hailo_write_action_list_params {
+    uint8_t *data;              // in
+    size_t size;                // in
+    uint64_t dma_address;       // out
+};
+
 /* structure used in ioctl HAILO_DESC_LIST_BIND_VDMA_BUFFER */
 struct hailo_desc_list_program_params {
     size_t buffer_handle;       // in
@@ -508,6 +515,7 @@ struct hailo_vdma_launch_transfer_params {
 
 /* structure used in ioctl HAILO_SOC_CONNECT */
 struct hailo_soc_connect_params {
+    uint16_t port_number;           // in
     uint8_t input_channel_index;    // out
     uint8_t output_channel_index;   // out
     uintptr_t input_desc_handle;    // in
@@ -522,6 +530,7 @@ struct hailo_soc_close_params {
 
 /* structure used in ioctl HAILO_PCI_EP_ACCEPT */
 struct hailo_pci_ep_accept_params {
+    uint16_t port_number;           // in
     uint8_t input_channel_index;    // out
     uint8_t output_channel_index;   // out
     uintptr_t input_desc_handle;    // in
@@ -562,6 +571,7 @@ struct tCompatibleHailoIoctlData
         struct hailo_soc_close_params SocCloseParams;
         struct hailo_pci_ep_accept_params AcceptParams;
         struct hailo_pci_ep_close_params PciEpCloseParams;
+        struct hailo_write_action_list_params WriteActionListParams;
     } Buffer;
 };
 #endif // _MSC_VER
@@ -632,6 +642,7 @@ enum hailo_nnc_ioctl_code {
     HAILO_DISABLE_NOTIFICATION_CODE,
     HAILO_READ_LOG_CODE,
     HAILO_RESET_NN_CORE_CODE,
+    HAILO_WRITE_ACTION_LIST_CODE,
 
     // Must be last
     HAILO_NNC_IOCTL_MAX_NR
@@ -642,6 +653,7 @@ enum hailo_nnc_ioctl_code {
 #define HAILO_DISABLE_NOTIFICATION      _IO_(HAILO_NNC_IOCTL_MAGIC,    HAILO_DISABLE_NOTIFICATION_CODE)
 #define HAILO_READ_LOG                  _IOWR_(HAILO_NNC_IOCTL_MAGIC,  HAILO_READ_LOG_CODE,                   struct hailo_read_log_params)
 #define HAILO_RESET_NN_CORE             _IO_(HAILO_NNC_IOCTL_MAGIC,    HAILO_RESET_NN_CORE_CODE)
+#define HAILO_WRITE_ACTION_LIST         _IOW_(HAILO_NNC_IOCTL_MAGIC,    HAILO_WRITE_ACTION_LIST_CODE,     struct hailo_write_action_list_params)
 
 enum hailo_soc_ioctl_code {
     HAILO_SOC_IOCTL_CONNECT_CODE,

drivers/media/pci/hailo/common/hailo_resource.c

@@ -1,24 +1,31 @@
 // SPDX-License-Identifier: MIT
 /**
- * Copyright (c) 2019-2022 Hailo Technologies Ltd. All rights reserved.
+ * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved.
  **/
 
 #include "hailo_resource.h"
 
+#include "utils.h"
+
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/types.h>
 #include <linux/kernel.h>
 
+#define ALIGN_TO_32_BIT(addr) ((addr) & (~((uintptr_t)0x3)))
 
 u8 hailo_resource_read8(struct hailo_resource *resource, size_t offset)
 {
-    return ioread8((u8*)resource->address + offset);
+    u32 val = ioread32((u8*)ALIGN_TO_32_BIT(resource->address + offset));
+    u64 offset_in_bits = BITS_IN_BYTE * ((resource->address + offset) - ALIGN_TO_32_BIT(resource->address + offset));
+    return (u8)READ_BITS_AT_OFFSET(BYTE_SIZE * BITS_IN_BYTE, offset_in_bits, val);
 }
 
 u16 hailo_resource_read16(struct hailo_resource *resource, size_t offset)
 {
-    return ioread16((u8*)resource->address + offset);
+    u32 val = ioread32((u8*)ALIGN_TO_32_BIT(resource->address + offset));
+    u64 offset_in_bits = BITS_IN_BYTE * ((resource->address + offset) - ALIGN_TO_32_BIT(resource->address + offset));
+    return (u16)READ_BITS_AT_OFFSET(WORD_SIZE * BITS_IN_BYTE, offset_in_bits, val);
 }
 
 u32 hailo_resource_read32(struct hailo_resource *resource, size_t offset)
@@ -28,12 +35,18 @@ u32 hailo_resource_read32(struct hailo_resource *resource, size_t offset)
 
 void hailo_resource_write8(struct hailo_resource *resource, size_t offset, u8 value)
 {
-    iowrite8(value, (u8*)resource->address + offset);
+    u32 initial_val = ioread32((u8*)ALIGN_TO_32_BIT(resource->address + offset));
+    u64 offset_in_bits = BITS_IN_BYTE * ((resource->address + offset) - ALIGN_TO_32_BIT(resource->address + offset));
+    iowrite32(WRITE_BITS_AT_OFFSET(BYTE_SIZE * BITS_IN_BYTE, offset_in_bits, initial_val, value),
+        (u8*)ALIGN_TO_32_BIT(resource->address + offset));
 }
 
 void hailo_resource_write16(struct hailo_resource *resource, size_t offset, u16 value)
 {
-    iowrite16(value, (u8*)resource->address + offset);
+    u32 initial_val = ioread32((u8*)ALIGN_TO_32_BIT(resource->address + offset));
+    u64 offset_in_bits = BITS_IN_BYTE * ((resource->address + offset) - ALIGN_TO_32_BIT(resource->address + offset));
+    iowrite32(WRITE_BITS_AT_OFFSET(WORD_SIZE * BITS_IN_BYTE, offset_in_bits, initial_val, value),
+        (u8*)ALIGN_TO_32_BIT(resource->address + offset));
 }
 
 void hailo_resource_write32(struct hailo_resource *resource, size_t offset, u32 value)

drivers/media/pci/hailo/common/hailo_resource.h

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MIT
 /**
- * Copyright (c) 2019-2022 Hailo Technologies Ltd. All rights reserved.
+ * Copyright (c) 2019-2024 Hailo Technologies Ltd. All rights reserved.
  **/
 
 #ifndef _HAILO_COMMON_HAILO_RESOURCE_H_