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The baseline JIT compiler design involves tracing an EBB when its usage frequency exceeds a predetermined threshold. We then utilize a code generator to convert the instruction sequence into C code. The C code is subsequently compiled using mir, and the resulting target machine code is stored in the code cache for future utilization. The primary objective of introducing the baseline JIT compiler is to enhance the execution speed of RISC-V instructions with minimal modification. This implementation requires three additional components: a code generator, mir compiler, and code cache, while maintaining the original design of the interpreter. Furthermore, this baseline JIT compiler serves as the foundational target for future improvements. In addition, we have developed a Python script that effectively traces code templates and automatically generates JIT code templates. This approach eliminates the need for manually writing duplicated codey.
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@@ -18,3 +18,4 @@ build/map/ | |
tests/**/*.elf | ||
tests/arch-test-target/config.ini | ||
__pycache__/ | ||
src/jit_template.c |
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