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@qwe661234
qwe661234 committed Oct 29, 2023
1 parent 298fd6d commit 2f08fe6
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Showing 18 changed files with 108 additions and 71 deletions.
23 changes: 23 additions & 0 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,29 @@ CFLAGS += -D DEFAULT_STACK_ADDR=0xFFFFE000
# Set the default args starting address
CFLAGS += -D DEFAULT_ARGS_ADDR=0xFFFFF000


# Enable link-time optimization (LTO)
ENABLE_LTO ?= 1
ifeq ($(call has, LTO), 1)
ifeq ("$(CC_IS_CLANG)$(CC_IS_GCC)",)
$(warning LTO is only supported in clang and gcc.)
override ENABLE_LTO := 0
endif
endif
$(call set-feature, LTO)
ifeq ($(call has, LTO), 1)
ifeq ("$(CC_IS_GCC)", "1")
CFLAGS += -flto
endif
ifeq ("$(CC_IS_CLANG)", "1")
CFLAGS += -flto=thin -fsplit-lto-unit
LDFLAGS += -flto=thin
endif
endif

# Disable Intel's Control-flow Enforcement Technology (CET)
CFLAGS += $(CFLAGS_NO_CET)

OBJS_EXT :=

# Control and Status Register (CSR)
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27 changes: 16 additions & 11 deletions src/cache.c
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Expand Up @@ -614,15 +614,17 @@ bool cache_hot(struct cache *cache, uint32_t key)
#ifndef MIR
uint8_t *code_cache_lookup(cache_t *cache, uint32_t key)
{
if (!cache->capacity || hlist_empty(&cache->map->ht_list_head[cache_hash(key)]))
if (!cache->capacity ||
hlist_empty(&cache->map->ht_list_head[cache_hash(key)]))
return NULL;
#if RV32_HAS(ARC)
arc_entry_t *entry = NULL;
#ifdef __HAVE_TYPEOF
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)], ht_list)
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)],
ht_list)
#else
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)], ht_list,
arc_entry_t)
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)],
ht_list, arc_entry_t)
#endif
{
if (entry->key == key)
Expand All @@ -631,10 +633,11 @@ uint8_t *code_cache_lookup(cache_t *cache, uint32_t key)
#else
lfu_entry_t *entry = NULL;
#ifdef __HAVE_TYPEOF
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)], ht_list)
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)],
ht_list)
#else
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)], ht_list,
lfu_entry_t)
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)],
ht_list, lfu_entry_t)
#endif
{
if (entry->key == key)
Expand All @@ -658,15 +661,17 @@ uint8_t *code_cache_add(cache_t *cache,
uint64_t align)
{
cache->offset = align_to(cache->offset, align);
if (!cache->capacity || hlist_empty(&cache->map->ht_list_head[cache_hash(key)]))
if (!cache->capacity ||
hlist_empty(&cache->map->ht_list_head[cache_hash(key)]))
return NULL;
#if RV32_HAS(ARC)
arc_entry_t *entry = NULL;
#ifdef __HAVE_TYPEOF
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)], ht_list)
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)],
ht_list)
#else
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)], ht_list,
arc_entry_t)
hlist_for_each_entry (entry, &cache->map->ht_list_head[cache_hash(key)],
ht_list, arc_entry_t)
#endif
{
if (entry->key == key)
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18 changes: 8 additions & 10 deletions src/compile.c
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Original file line number Diff line number Diff line change
Expand Up @@ -154,10 +154,9 @@ static char funcbuf[128] = {0};
* code.
*/
RVOP(jal, {
GEN(" pc = PC;\n");
UPDATE_PC(ir->imm);
if (ir->rd) {
GEN(" rv->X[%u] = pc + 4;\n", ir->rd);
GEN(" rv->X[%u] = %u;\n", ir->rd, ir->pc + 4);
}
if (ir->branch_taken) {
NEXT_INSN(ir->pc + ir->imm);
Expand All @@ -167,10 +166,9 @@ RVOP(jal, {
})

RVOP(jalr, {
GEN(" pc = PC;\n");
GEN(" PC = (rv->X[%u] + %d) & ~1U;\n", ir->rs1, ir->imm);
if (ir->rd) {
GEN(" rv->X[%u] = pc + 4;\n", ir->rd);
GEN(" rv->X[%u] = %u;\n", ir->rd, ir->pc + 4);
}
END_INSN;
})
Expand Down Expand Up @@ -425,19 +423,19 @@ static void gen_fuse5(riscv_t *rv UNUSED, rv_insn_t *ir, char *gencode)
GEN("insn_%x:\n"
" cycle += 2;\n",
(ir->pc));
GEN(" memset((char *) m->mem_base + rv->X[rv_reg_a0], rv->X[rv_reg_a1], "
"rv->X[rv_reg_a2]); ");
END_INSN;
GEN(" rv->io.on_memset(rv);\n");
GEN(" rv->csr_cycle = cycle;\n");
GEN(" return true;\n");
}

static void gen_fuse6(riscv_t *rv UNUSED, rv_insn_t *ir, char *gencode)
{
GEN("insn_%x:\n"
" cycle += 2;\n",
(ir->pc));
GEN(" memcpy((char *) m->mem_base + rv->X[rv_reg_a0], (char *) "
"m->mem_base + rv->X[rv_reg_a1], rv->X[rv_reg_a2]);");
END_INSN;
GEN(" rv->io.on_memcpy(rv);\n");
GEN(" rv->csr_cycle = cycle;\n");
GEN(" return true;\n");
}

static void gen_fuse7(riscv_t *rv UNUSED, rv_insn_t *ir, char *gencode)
Expand Down
50 changes: 24 additions & 26 deletions src/emulate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -345,42 +345,24 @@ static bool do_fuse4(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)

/* memset */
static bool do_fuse5(riscv_t *rv,
const rv_insn_t *ir,
const rv_insn_t *ir UNUSED,
uint64_t cycle,
uint32_t PC)
uint32_t PC UNUSED)
{
cycle += 2;
memory_t *m = ((state_t *) rv->userdata)->mem;
memset((char *) m->mem_base + rv->X[rv_reg_a0], rv->X[rv_reg_a1],
rv->X[rv_reg_a2]);
PC = rv->X[rv_reg_ra] & ~1U;
if (unlikely(RVOP_NO_NEXT(ir))) {
rv->csr_cycle = cycle;
rv->PC = PC;
return true;
}
const rv_insn_t *next = ir->next;
MUST_TAIL return next->impl(rv, next, cycle, PC);
rv->io.on_memset(rv);
return true;
}

/* memcpy */
static bool do_fuse6(riscv_t *rv,
const rv_insn_t *ir,
const rv_insn_t *ir UNUSED,
uint64_t cycle,
uint32_t PC)
uint32_t PC UNUSED)
{
cycle += 2;
memory_t *m = ((state_t *) rv->userdata)->mem;
memcpy((char *) m->mem_base + rv->X[rv_reg_a0],
(char *) m->mem_base + rv->X[rv_reg_a1], rv->X[rv_reg_a2]);
PC = rv->X[rv_reg_ra] & ~1U;
if (unlikely(RVOP_NO_NEXT(ir))) {
rv->csr_cycle = cycle;
rv->PC = PC;
return true;
}
const rv_insn_t *next = ir->next;
MUST_TAIL return next->impl(rv, next, cycle, PC);
rv->io.on_memcpy(rv);
return true;
}

/* multiple shift immediate */
Expand Down Expand Up @@ -969,6 +951,22 @@ void ecall_handler(riscv_t *rv)
syscall_handler(rv);
}

void memset_handler(riscv_t *rv)
{
memory_t *m = ((state_t *) rv->userdata)->mem;
memset((char *) m->mem_base + rv->X[rv_reg_a0], rv->X[rv_reg_a1],
rv->X[rv_reg_a2]);
rv->PC = rv->X[rv_reg_ra] & ~1U;
}

void memcpy_handler(riscv_t *rv)
{
memory_t *m = ((state_t *) rv->userdata)->mem;
memcpy((char *) m->mem_base + rv->X[rv_reg_a0],
(char *) m->mem_base + rv->X[rv_reg_a1], rv->X[rv_reg_a2]);
rv->PC = rv->X[rv_reg_ra] & ~1U;
}

void dump_registers(riscv_t *rv, char *out_file_path)
{
FILE *f;
Expand Down
2 changes: 2 additions & 0 deletions src/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -216,6 +216,8 @@ int main(int argc, char **args)
/* system */
.on_ecall = ecall_handler,
.on_ebreak = ebreak_handler,
.on_memcpy = memcpy_handler,
.on_memset = memset_handler,
.allow_misalign = opt_misaligned,
};

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6 changes: 3 additions & 3 deletions src/riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -127,11 +127,11 @@ riscv_t *rv_create(const riscv_io_t *io,

#if !RV32_HAS(JIT)
/* initialize the block map */
block_map_init(&rv->block_map, 10);
block_map_init(&rv->block_map, BLOCK_MAP_CAPACITY_BITS);
#else
rv->block_cache = cache_create(10);
rv->block_cache = cache_create(BLOCK_MAP_CAPACITY_BITS);
#ifdef MIR
rv->code_cache = cache_create(10);
rv->code_cache = cache_create(BLOCK_MAP_CAPACITY_BITS);
#endif
#endif
/* reset */
Expand Down
14 changes: 11 additions & 3 deletions src/riscv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ enum {
#define MSTATUS_MPIE (1 << MSTATUS_MPIE_SHIFT)
#define MSTATUS_MPP (3 << MSTATUS_MPP_SHIFT)

#define BLOCK_MAP_CAPACITY_BITS 10
#define BLOCK_MAP_CAPACITY_BITS 11

/* forward declaration for internal structure */
typedef struct riscv_internal riscv_t;
Expand All @@ -105,7 +105,8 @@ typedef void (*riscv_mem_write_b)(riscv_word_t addr, riscv_byte_t data);
/* system instruction handlers */
typedef void (*riscv_on_ecall)(riscv_t *rv);
typedef void (*riscv_on_ebreak)(riscv_t *rv);

typedef void (*riscv_on_memset)(riscv_t *rv);
typedef void (*riscv_on_memcpy)(riscv_t *rv);
/* RISC-V emulator I/O interface */
typedef struct {
/* memory read interface */
Expand All @@ -122,7 +123,8 @@ typedef struct {
/* system */
riscv_on_ecall on_ecall;
riscv_on_ebreak on_ebreak;

riscv_on_memset on_memset;
riscv_on_memcpy on_memcpy;
/* enable misaligned memory access */
bool allow_misalign;
} riscv_io_t;
Expand Down Expand Up @@ -169,6 +171,12 @@ void syscall_handler(riscv_t *rv);
/* environment call handler */
void ecall_handler(riscv_t *rv);

/* memset handler */
void memset_handler(riscv_t *rv);

/* memcpy handler */
void memcpy_handler(riscv_t *rv);

/* dump registers as JSON to out_file_path */
void dump_registers(riscv_t *rv, char *out_file_path);

Expand Down
39 changes: 21 additions & 18 deletions src/rv32_template.c
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Original file line number Diff line number Diff line change
Expand Up @@ -32,14 +32,15 @@ RVOP(jal, {
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
struct rv_insn *taken = ir->branch_taken;
if (taken) {
#if !RV32_HAS(JIT)
MUST_TAIL return taken->impl(rv, taken, cycle, PC);
#else
if (!cache_get(rv->block_cache, PC)) {
clear_flag = true;
goto end_insn;
#if RV32_HAS(JIT)
if (!cache_get(rv->block_cache, PC)) {
clear_flag = true;
goto end_insn;
}
if (cache_hot(rv->block_cache, PC))
goto end_insn;
#endif
MUST_TAIL return taken->impl(rv, taken, cycle, PC);
}
end_insn:
rv->csr_cycle = cycle;
Expand Down Expand Up @@ -841,14 +842,15 @@ RVOP(cjal, {
RV_EXC_MISALIGN_HANDLER(PC, insn, true, 0);
struct rv_insn *taken = ir->branch_taken;
if (taken) {
#if !RV32_HAS(JIT)
MUST_TAIL return taken->impl(rv, taken, cycle, PC);
#else
if (!cache_get(rv->block_cache, PC)) {
clear_flag = true;
goto end_insn;
#if RV32_HAS(JIT)
if (!cache_get(rv->block_cache, PC)) {
clear_flag = true;
goto end_insn;
}
if (cache_hot(rv->block_cache, PC))
goto end_insn;
#endif
MUST_TAIL return taken->impl(rv, taken, cycle, PC);
}
end_insn:
rv->csr_cycle = cycle;
Expand Down Expand Up @@ -921,14 +923,15 @@ RVOP(cj, {
RV_EXC_MISALIGN_HANDLER(PC, insn, true, 0);
struct rv_insn *taken = ir->branch_taken;
if (taken) {
#if !RV32_HAS(JIT)
MUST_TAIL return taken->impl(rv, taken, cycle, PC);
#else
if (!cache_get(rv->block_cache, PC)) {
clear_flag = true;
goto end_insn;
#if RV32_HAS(JIT)
if (!cache_get(rv->block_cache, PC)) {
clear_flag = true;
goto end_insn;
}
if (cache_hot(rv->block_cache, PC))
goto end_insn;
#endif
MUST_TAIL return taken->impl(rv, taken, cycle, PC);
}
end_insn:
rv->csr_cycle = cycle;
Expand Down

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